drm/i915: Clean up 10bit precision palette defines

Use consistent bit definitions for the 10bit precision palette bits.
We just define these alongside the ilk/snb register definitions and
point to those from the ivb+ defines.

Also use the these appropriately in the LUT entry pack/unpack
functions.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221114153732.11773-3-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 2cf92bc55e8dd00367ae24485506974b2df4b422..05257d92408b8c2e4847f5ab24bc4ea4cda2c131 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -471,16 +471,16 @@ static u16 i965_lut_11p6_max_pack(u32 val)
 
 static u32 ilk_lut_10(const struct drm_color_lut *color)
 {
-       return drm_color_lut_extract(color->red, 10) << 20 |
-               drm_color_lut_extract(color->green, 10) << 10 |
-               drm_color_lut_extract(color->blue, 10);
+       return REG_FIELD_PREP(PREC_PALETTE_10_RED_MASK, drm_color_lut_extract(color->red, 10)) |
+               REG_FIELD_PREP(PREC_PALETTE_10_GREEN_MASK, drm_color_lut_extract(color->green, 10)) |
+               REG_FIELD_PREP(PREC_PALETTE_10_BLUE_MASK, drm_color_lut_extract(color->blue, 10));
 }
 
 static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
 {
-       entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
-       entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
-       entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+       entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_RED_MASK, val), 10);
+       entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_GREEN_MASK, val), 10);
+       entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_10_BLUE_MASK, val), 10);
 }
 
 /* ilk+ "12.4" interpolated format (high 10 bits) */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6caa6ebefb417160200a700d99532e3af97db1ab..f2a696ee69dc2422c1fa60b81ba70be1af2d2448 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5313,9 +5313,10 @@
 /* ilk/snb precision palette */
 #define _PREC_PALETTE_A           0x4b000
 #define _PREC_PALETTE_B           0x4c000
-#define   PREC_PALETTE_RED_MASK   REG_GENMASK(29, 20)
-#define   PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10)
-#define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
+/* 10bit mode */
+#define   PREC_PALETTE_10_RED_MASK             REG_GENMASK(29, 20)
+#define   PREC_PALETTE_10_GREEN_MASK           REG_GENMASK(19, 10)
+#define   PREC_PALETTE_10_BLUE_MASK            REG_GENMASK(9, 0)
 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4)
 
 #define  _PREC_PIPEAGCMAX              0x4d000
@@ -7545,12 +7546,10 @@ enum skl_power_gate {
 #define _PAL_PREC_DATA_A       0x4A404
 #define _PAL_PREC_DATA_B       0x4AC04
 #define _PAL_PREC_DATA_C       0x4B404
+/* see PREC_PALETTE_* for the bits */
 #define _PAL_PREC_GC_MAX_A     0x4A410
 #define _PAL_PREC_GC_MAX_B     0x4AC10
 #define _PAL_PREC_GC_MAX_C     0x4B410
-#define   PREC_PAL_DATA_RED_MASK       REG_GENMASK(29, 20)
-#define   PREC_PAL_DATA_GREEN_MASK     REG_GENMASK(19, 10)
-#define   PREC_PAL_DATA_BLUE_MASK      REG_GENMASK(9, 0)
 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420
 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420