clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs

The custom clock driver that models the PLL clocks on R-Car Gen4
supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M.
R-Car S4-8 uses integer and fractional multiplication fields that are
one bit larger resp. smaller, and a slightly different formula.

Extend the existing support to fractional 9.24 PLL, and introduce new
clock types and helper macros to describe these PLLs.

Note that there is no use case for variable fractional 9.24 PLLs yet, as
the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode.
Hence the PLL is always modeled as a fixed PLL, regardless of the
description,

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/5684eda1260435c8eceabc274e0b18cb280a6341.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 1f3dddbd294a572b0ec09a5cb4943029addf314b..d3db602d7c5ec6171de7526d2fafd8e380a2b728 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -56,6 +56,10 @@ static u32 cpg_mode __initdata;
 #define CPG_PLLxCR0_NI8                GENMASK(27, 20) /* Integer mult. factor */
 #define CPG_PLLxCR1_NF25       GENMASK(24, 0)  /* Fractional mult. factor */
 
+/* Fractional 9.24 PLL */
+#define CPG_PLLxCR0_NI9                GENMASK(28, 20) /* Integer mult. factor */
+#define CPG_PLLxCR1_NF24       GENMASK(23, 0)  /* Fractional mult. factor */
+
 #define CPG_PLLxCR_STC         GENMASK(30, 24) /* R_Car V3U PLLxCR */
 
 #define CPG_RPCCKCR            0x874   /* RPC Clock Freq. Control Register */
@@ -189,6 +193,30 @@ static const struct clk_ops cpg_pll_v8_25_clk_ops = {
        .set_rate = cpg_pll_8_25_clk_set_rate,
 };
 
+static unsigned long cpg_pll_9_24_clk_recalc_rate(struct clk_hw *hw,
+                                                 unsigned long parent_rate)
+{
+       struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
+       u32 cr0 = readl(pll_clk->pllcr0_reg);
+       unsigned int ni, nf;
+       unsigned long rate;
+
+       ni = FIELD_GET(CPG_PLLxCR0_NI9, cr0) + 1;
+       rate = parent_rate * ni;
+       if (cr0 & CPG_PLLxCR0_SSMODE_FM) {
+               nf = FIELD_GET(CPG_PLLxCR1_NF24, readl(pll_clk->pllcr1_reg));
+               rate += mul_u64_u32_shr(parent_rate, nf, 24);
+       } else {
+               rate *= 2;
+       }
+
+       return rate;
+}
+
+static const struct clk_ops cpg_pll_f9_24_clk_ops = {
+       .recalc_rate = cpg_pll_9_24_clk_recalc_rate,
+};
+
 static struct clk * __init cpg_pll_clk_register(const char *name,
                                                const char *parent_name,
                                                void __iomem *base,
@@ -461,6 +489,14 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
                                            base, core->offset,
                                            &cpg_pll_v8_25_clk_ops);
 
+       case CLK_TYPE_GEN4_PLL_V9_24:
+               /* Variable fractional 9.24 is not yet supported, using fixed */
+               fallthrough;
+       case CLK_TYPE_GEN4_PLL_F9_24:
+               return cpg_pll_clk_register(core->name, __clk_get_name(parent),
+                                           base, core->offset,
+                                           &cpg_pll_f9_24_clk_ops);
+
        case CLK_TYPE_GEN4_Z:
                return cpg_z_clk_register(core->name, __clk_get_name(parent),
                                          base, core->div, core->offset);

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index 69436309f19dfff2648a716879117920a1f503c3..80a455e62cc1321e2f51d7c36d0fe3a1772746c2 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -21,6 +21,8 @@ enum rcar_gen4_clk_types {
        CLK_TYPE_GEN4_PLL6,
        CLK_TYPE_GEN4_PLL_F8_25,        /* Fixed fractional 8.25 PLL */
        CLK_TYPE_GEN4_PLL_V8_25,        /* Variable fractional 8.25 PLL */
+       CLK_TYPE_GEN4_PLL_F9_24,        /* Fixed fractional 9.24 PLL */
+       CLK_TYPE_GEN4_PLL_V9_24,        /* Variable fractional 9.24 PLL */
        CLK_TYPE_GEN4_SDSRC,
        CLK_TYPE_GEN4_SDH,
        CLK_TYPE_GEN4_SD,
@@ -55,6 +57,12 @@ enum rcar_gen4_clk_types {
 #define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent)  \
        DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx)
 
+#define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent)  \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F9_24, _parent, .offset = _idx)
+
+#define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent)  \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx)
+
 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)  \
        DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)