wc->dlid_path_bits = cqe->dlid_path_bits;
        wc->port_num = cqe->port_num;
        wc->vendor_err = cqe->vendor_err;
+       wc->network_hdr_type = cqe->network_hdr_type;
 
        /* Update shared ring state */
        pvrdma_idx_ring_inc(&cq->ring_state->rx.cons_head, cq->ibcq.cqe);
 
        PVRDMA_WC_IP_CSUM_OK            = 1 << 3,
        PVRDMA_WC_WITH_SMAC             = 1 << 4,
        PVRDMA_WC_WITH_VLAN             = 1 << 5,
-       PVRDMA_WC_FLAGS_MAX             = PVRDMA_WC_WITH_VLAN,
+       PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6,
+       PVRDMA_WC_FLAGS_MAX             = PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
 };
 
 struct pvrdma_alloc_ucontext_resp {
        __u8 dlid_path_bits;
        __u8 port_num;
        __u8 smac[6];
-       __u8 reserved2[7]; /* Pad to next power of 2 (64). */
+       __u8 network_hdr_type;
+       __u8 reserved2[6]; /* Pad to next power of 2 (64). */
 };
 
 #endif /* __VMW_PVRDMA_ABI_H__ */