drm/amd/display: fix index and union overwrite in compressor

  Fixing 2 bugs in compressor:
- array out of bounds due to incorrect index
- compressor options always 0 due to union overwrite

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 1e59f4e31a6a201d1cddde23b4790bcec637b58a..9759d8e790a3bc6232164263d19bde9d7dd0f304 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -198,7 +198,7 @@ void dce110_compressor_enable_fbc(
                /* Keep track of enum controller_id FBC is attached to */
                compressor->is_enabled = true;
                compressor->attached_inst = params->inst;
-               cp110->offsets = reg_offsets[params->inst - 1];
+               cp110->offsets = reg_offsets[params->inst];
 
                /*Toggle it as there is bug in HW */
                set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
@@ -469,6 +469,7 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
        struct dc_context *ctx)
 {
 
+       compressor->base.options.raw = 0;
        compressor->base.options.bits.FBC_SUPPORT = true;
 
        /* for dce 11 always use one dram channel for lpt */
@@ -490,7 +491,6 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
        compressor->base.allocated_size = 0;
        compressor->base.preferred_requested_size = 0;
        compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-       compressor->base.options.raw = 0;
        compressor->base.banks_num = 0;
        compressor->base.raw_size = 0;
        compressor->base.channel_interleave_size = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
index 22a5aba073ca9e06e3e7035cec08311f1ba1d47b..75af2125344b5ef07c410b7af2669620fd8baabc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
@@ -404,7 +404,7 @@ void dce112_compressor_enable_fbc(
                /* Keep track of enum controller_id FBC is attached to */
                compressor->is_enabled = true;
                compressor->attached_inst = params->inst;
-               cp110->offsets = reg_offsets[params->inst - 1];
+               cp110->offsets = reg_offsets[params->inst];
 
                /*Toggle it as there is bug in HW */
                set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
@@ -797,6 +797,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
        struct dc_bios *bp = ctx->dc_bios;
        struct embedded_panel_info panel_info;
 
+       compressor->base.options.raw = 0;
        compressor->base.options.bits.FBC_SUPPORT = true;
        compressor->base.options.bits.LPT_SUPPORT = true;
         /* For DCE 11 always use one DRAM channel for LPT */
@@ -817,7 +818,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
        compressor->base.allocated_size = 0;
        compressor->base.preferred_requested_size = 0;
        compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-       compressor->base.options.raw = 0;
        compressor->base.banks_num = 0;
        compressor->base.raw_size = 0;
        compressor->base.channel_interleave_size = 0;

diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
index eeedb7c4fe53f130a140faf63294a7696b242055..77626d7624c626bdea9a2c5bd792fa44f4b0d60c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
@@ -407,7 +407,7 @@ void dce80_compressor_enable_fbc(
                /* Keep track of enum controller_id FBC is attached to */
                compressor->is_enabled = true;
                compressor->attached_inst = params->inst;
-               cp80->offsets = reg_offsets[params->inst - 1];
+               cp80->offsets = reg_offsets[params->inst];
 
                /*Toggle it as there is bug in HW */
                set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
@@ -777,6 +777,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
        struct dc_bios *bp = ctx->dc_bios;
        struct embedded_panel_info panel_info;
 
+       compressor->base.options.raw = 0;
        compressor->base.options.bits.FBC_SUPPORT = true;
        compressor->base.options.bits.LPT_SUPPORT = true;
         /* For DCE 11 always use one DRAM channel for LPT */
@@ -797,7 +798,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
        compressor->base.allocated_size = 0;
        compressor->base.preferred_requested_size = 0;
        compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-       compressor->base.options.raw = 0;
        compressor->base.banks_num = 0;
        compressor->base.raw_size = 0;
        compressor->base.channel_interleave_size = 0;