drm/amd/display: Remove hardmax usage for dcn401

[WHY&HOW]
Hardmax message will be retired for dcn4, so this removes it.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index c453c5f15ce74907dab7898319756e58b70d57a0..cce425dd62d2d55eaece4016474ae3fb88b3d85f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -931,12 +931,12 @@ static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned
 static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
                struct clk_mgr *clk_mgr_base,
                struct dc_state *context,
+               struct dc_clocks *new_clocks,
                bool safe_to_lower)
 {
        struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
        struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
        struct dc *dc = clk_mgr_base->ctx->dc;
-       struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
        struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
        bool enter_display_off = false;
        bool update_active_fclk = false;
@@ -1218,13 +1218,13 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 static unsigned int dcn401_build_update_display_clocks_sequence(
                struct clk_mgr *clk_mgr_base,
                struct dc_state *context,
+               struct dc_clocks *new_clocks,
                bool safe_to_lower)
 {
        struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
        struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
        struct dc *dc = clk_mgr_base->ctx->dc;
        struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
-       struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
        struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
        bool force_reset = false;
        bool update_dispclk = false;
@@ -1375,6 +1375,7 @@ static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
        /* build bandwidth related clocks update sequence */
        num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
                        context,
+                       &context->bw_ctx.bw.dcn.clk,
                        safe_to_lower);
 
        /* execute sequence */
@@ -1383,6 +1384,7 @@ static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
        /* build display related clocks update sequence */
        num_steps = dcn401_build_update_display_clocks_sequence(clk_mgr_base,
                        context,
+                       &context->bw_ctx.bw.dcn.clk,
                        safe_to_lower);
 
        /* execute sequence */
@@ -1474,33 +1476,34 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
 {
        struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+       const struct dc *dc = clk_mgr->base.ctx->dc;
+       struct dc_state *context = dc->current_state;
+       struct dc_clocks new_clocks;
+       int num_steps;
 
        if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
                return;
 
+       /* build clock update */
+       memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
+
        if (current_mode) {
-               if (clk_mgr_base->clks.p_state_change_support)
-                       dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-                                       khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
-               else
-                       dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-                                       clk_mgr_base->bw_params->max_memclk_mhz);
+               new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;
+               new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;
+               new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
        } else {
-               dcn401_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-                               clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+               new_clocks.dramclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz * 1000;
+               new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz;
+               new_clocks.p_state_change_support = true;
        }
-}
 
-/* Set max memclk to highest DPM value */
-static void dcn401_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
-{
-       struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-
-       if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
-               return;
+       num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
+                       context,
+                       &new_clocks,
+                       true);
 
-       dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
-                       clk_mgr_base->bw_params->max_memclk_mhz);
+       /* execute sequence */
+       dcn401_execute_block_sequence(clk_mgr_base,     num_steps);
 }
 
 /* Get current memclk states, update bounding box */
@@ -1631,7 +1634,6 @@ static struct clk_mgr_funcs dcn401_funcs = {
                .init_clocks = dcn401_init_clocks,
                .notify_wm_ranges = dcn401_notify_wm_ranges,
                .set_hard_min_memclk = dcn401_set_hard_min_memclk,
-               .set_hard_max_memclk = dcn401_set_hard_max_memclk,
                .get_memclk_states_from_smu = dcn401_get_memclk_states_from_smu,
                .are_clock_states_equal = dcn401_are_clock_states_equal,
                .enable_pme_wa = dcn401_enable_pme_wa,

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f07b13ad4eadee2ae862bd79d12fd960b55f9172..b71c4d8e73dde28334d26a48e8252b02b0d91796 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -5462,9 +5462,10 @@ static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memcl
                        hubp->funcs->set_blank_regs(hubp, true);
                }
        }
-
-       dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
-       dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
+       if (dc->clk_mgr->funcs->set_max_memclk)
+               dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
+       if (dc->clk_mgr->funcs->set_min_memclk)
+               dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                pipe = &context->res_ctx.pipe_ctx[i];
@@ -5513,7 +5514,7 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
 
        if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
                if (p_state_change_support) {
-                       if (funcMin <= softMax)
+                       if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)
                                dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
                        // else: No-Op
                } else {
@@ -5523,7 +5524,7 @@ void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
                }
        } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
                if (p_state_change_support) {
-                       if (funcMin <= softMax)
+                       if (funcMin <= softMax && dc->clk_mgr->funcs->set_max_memclk)
                                dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
                        // else: No-Op
                } else {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index f4c1547a368fa64a262d0224408a5c4f3c89bfa7..779960278a5ce2cc179f376ed4abfe619b971126 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -416,9 +416,6 @@ void dcn401_init_hw(struct dc *dc)
        if (dc->clk_mgr->funcs->notify_wm_ranges)
                dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 
-       if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
-               dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
-
        if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
                dc->res_pool->hubbub->funcs->force_pstate_change_control(
                                dc->res_pool->hubbub, false, false);