ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care of

ARMv8M introduces support for Security extension to M class, among
other things it affects exception handling, especially, encoding of
EXC_RETURN.

The new bits have been added:

Bit [6]	Secure or Non-secure stack
Bit [5]	Default callee register stacking
Bit [0]	Exception Secure

which conflicts with hard-coded value of EXC_RETURN:

In fact, we only care of few bits:

Bit [3]	 Mode (0 - Handler, 1 - Thread)
Bit [2]	 Stack pointer selection (0 - Main, 1 - Process)

We can toggle only those bits and left other bits as they were on
exception entry.

It is basically, what patch does - saves EXC_RETURN when we do
transition form Thread to Handler mode (it is first svc), so later
saved value is used instead of EXC_RET_THREADMODE_PROCESSSTACK.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
index 187ccf6496ad61c222dc6e53102ec8a5b6ccf881..2cb00d15831b93e9e10164134d1f72cdb64c4bb0 100644 (file)
--- a/arch/arm/include/asm/v7m.h
+++ b/arch/arm/include/asm/v7m.h
@@ -49,7 +49,7 @@
  * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
  */
 #define EXC_RET_STACK_MASK                     0x00000004
-#define EXC_RET_THREADMODE_PROCESSSTACK                0xfffffffd
+#define EXC_RET_THREADMODE_PROCESSSTACK                (3 << 2)
 
 /* Cache related definitions */
 

diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 773424843d6efcc2ebeb0ec0cfa88d67643213cc..62db1c9746cbc83607c9eaeb45b52a294b94e36e 100644 (file)
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -127,7 +127,8 @@
          */
        .macro  v7m_exception_slow_exit ret_r0
        cpsid   i
-       ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
+       ldr     lr, =exc_ret
+       ldr     lr, [lr]
 
        @ read original r12, sp, lr, pc and xPSR
        add     r12, sp, #S_IP

diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
index abcf4784852593397daf3b1e6cf5d70cf47660e0..19d2dcd6530dc351188bd6c7785705e36e9e64d7 100644 (file)
--- a/arch/arm/kernel/entry-v7m.S
+++ b/arch/arm/kernel/entry-v7m.S
@@ -146,3 +146,7 @@ ENTRY(vector_table)
        .rept   CONFIG_CPU_V7M_NUM_IRQ
        .long   __irq_entry             @ External Interrupts
        .endr
+       .align  2
+       .globl  exc_ret
+exc_ret:
+       .space  4

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 47a5acc644333f7f995293ef6b3dc6fb3527270a..92e84181933ad96fec9bcb488e148b2c7874310d 100644 (file)
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -139,6 +139,9 @@ __v7m_setup_cont:
        cpsie   i
        svc     #0
 1:     cpsid   i
+       ldr     r0, =exc_ret
+       orr     lr, lr, #EXC_RET_THREADMODE_PROCESSSTACK
+       str     lr, [r0]
        ldmia   sp, {r0-r3, r12}
        str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
        mov     lr, r6                  @ restore LR