drm/amd/display: Convert 10kHz clks from PPLib into kHz

The driver is expecting clock frequency in kHz, while SMU returns
the values in 10kHz, which causes the bandwidth validation to fail

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index a87a5946798c45e8b3afe128148eea84e99d9bf1..a19df20b557b38a1ffa39ffe4f1b2578384ca41a 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -267,8 +267,9 @@ static void pp_to_dc_clock_levels_with_latency(
                        DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
        for (i = 0; i < clk_level_info->num_levels; i++) {
-               DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-               clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+               DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+               /* translate 10kHz to kHz */
+               clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
                clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
        }
 }
@@ -294,8 +295,9 @@ static void pp_to_dc_clock_levels_with_voltage(
                        DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 
        for (i = 0; i < clk_level_info->num_levels; i++) {
-               DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
-               clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
+               DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+               /* translate 10kHz to kHz */
+               clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
                clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
        }
 }
@@ -471,8 +473,9 @@ bool dm_pp_get_static_clocks(
                return false;
 
        static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state;
-       static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
-       static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
+       /* translate 10kHz to kHz */
+       static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
+       static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
 
        return true;
 }