riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index a2c72b385a90511d75a045b297dac4f5fafee16b..cf1ee98454d6f1cd734253e1d2ea05dc3c41c88a 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -354,9 +354,17 @@
 };
 
 &syscrg {
-       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
+       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+                         <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+                         <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+                         <&syscrg JH7110_SYSCLK_QSPI_REF>,
+                         <&syscrg JH7110_SYSCLK_CPU_CORE>,
                          <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-       assigned-clock-rates = <500000000>, <1500000000>;
+       assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+                                <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+       assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
 };
 
 &sysgpio {