clk: renesas: rcar-gen4: Add support for variable fractional PLLs

The custom clock driver that models PLL clocks on R-Car Gen4 supports
PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same
control register layout.

Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new
clock type and helper macro to describe these PLLs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 8bc96f22e41fdfcab754720bc4dd9fb3c6f3b36e..7f95231ccee8bd11a713ba37e7e0b18b0b99c21d 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -188,13 +188,16 @@ static const struct clk_ops cpg_pll_v8_25_clk_ops = {
 static struct clk * __init cpg_pll_clk_register(const char *name,
                                                const char *parent_name,
                                                void __iomem *base,
-                                               unsigned int cr0_offset,
-                                               unsigned int cr1_offset,
                                                unsigned int index)
-
 {
-       struct cpg_pll_clk *pll_clk;
+       static const struct { u16 cr0, cr1; } pll_cr_offsets[] __initconst = {
+               [2 - 2] = { CPG_PLL2CR0, CPG_PLL2CR1 },
+               [3 - 2] = { CPG_PLL3CR0, CPG_PLL3CR1 },
+               [4 - 2] = { CPG_PLL4CR0, CPG_PLL4CR1 },
+               [6 - 2] = { CPG_PLL6CR0, CPG_PLL6CR1 },
+       };
        struct clk_init_data init = {};
+       struct cpg_pll_clk *pll_clk;
        struct clk *clk;
 
        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
@@ -207,8 +210,8 @@ static struct clk * __init cpg_pll_clk_register(const char *name,
        init.num_parents = 1;
 
        pll_clk->hw.init = &init;
-       pll_clk->pllcr0_reg = base + cr0_offset;
-       pll_clk->pllcr1_reg = base + cr1_offset;
+       pll_clk->pllcr0_reg = base + pll_cr_offsets[index - 2].cr0;
+       pll_clk->pllcr1_reg = base + pll_cr_offsets[index - 2].cr1;
        pll_clk->pllecr_reg = base + CPG_PLLECR;
        pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
 
@@ -410,7 +413,7 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
                 * modes.
                 */
                return cpg_pll_clk_register(core->name, __clk_get_name(parent),
-                                           base, CPG_PLL2CR0, CPG_PLL2CR1, 2);
+                                           base, 2);
 
        case CLK_TYPE_GEN4_PLL2:
                mult = cpg_pll_config->pll2_mult;
@@ -442,6 +445,10 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
                mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
                break;
 
+       case CLK_TYPE_GEN4_PLL_V8_25:
+               return cpg_pll_clk_register(core->name, __clk_get_name(parent),
+                                           base, core->offset);
+
        case CLK_TYPE_GEN4_Z:
                return cpg_z_clk_register(core->name, __clk_get_name(parent),
                                          base, core->div, core->offset);

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index a277cf0598c4e6670a1d49ffd38ede21a874282a..d02e61911bfc6903f22b23d28d20a75de8d871a9 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -19,6 +19,7 @@ enum rcar_gen4_clk_types {
        CLK_TYPE_GEN4_PLL4,
        CLK_TYPE_GEN4_PLL5,
        CLK_TYPE_GEN4_PLL6,
+       CLK_TYPE_GEN4_PLL_V8_25,        /* Variable fractional 8.25 PLL */
        CLK_TYPE_GEN4_SDSRC,
        CLK_TYPE_GEN4_SDH,
        CLK_TYPE_GEN4_SD,
@@ -47,6 +48,9 @@ enum rcar_gen4_clk_types {
 #define DEF_GEN4_OSC(_name, _id, _parent, _div)                \
        DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
 
+#define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent)  \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx)
+
 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)  \
        DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)