mfd: bd71828, bd71815: Prepare for power-supply support

Add core support for ROHM BD718(15/28/78) PMIC's charger blocks.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20250821-bd71828-charger-v3-1-cc74ac4e0fb9@kemnade.info
Signed-off-by: Lee Jones <lee@kernel.org>

diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c
index a14b7aa69c3c61d51f2aeeae9afdf222310d63e3..84a64c3b9c9f52e663855c89ed78ede9a7c21f55 100644 (file)
--- a/drivers/mfd/rohm-bd71828.c
+++ b/drivers/mfd/rohm-bd71828.c
@@ -45,8 +45,8 @@ static const struct resource bd71828_rtc_irqs[] = {
 
 static const struct resource bd71815_power_irqs[] = {
        DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
@@ -56,7 +56,7 @@ static const struct resource bd71815_power_irqs[] = {
        DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
@@ -87,10 +87,10 @@ static const struct resource bd71815_power_irqs[] = {
        DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
        DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-bat-low-res"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-bat-low-det"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"),
-       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"),
+       DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"),
 };
 
 static const struct mfd_cell bd71815_mfd_cells[] = {
@@ -109,7 +109,30 @@ static const struct mfd_cell bd71815_mfd_cells[] = {
        },
 };
 
-static const struct mfd_cell bd71828_mfd_cells[] = {
+static const struct resource bd71828_power_irqs[] = {
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE,
+                            "bd71828-chg-done"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES,
+                            "bd71828-vbat-normal"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES,
+                            "bd71828-btemp-warm"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET,
+                            "bd71828-temp-hi"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES,
+                            "bd71828-temp-norm"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET,
+                            "bd71828-temp-125-over"),
+       DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES,
+                            "bd71828-temp-125-under"),
+};
+
+static struct mfd_cell bd71828_mfd_cells[] = {
        { .name = "bd71828-pmic", },
        { .name = "bd71828-gpio", },
        { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" },
@@ -118,8 +141,11 @@ static const struct mfd_cell bd71828_mfd_cells[] = {
         * BD70528 clock gate are the register address and mask.
         */
        { .name = "bd71828-clk", },
-       { .name = "bd71827-power", },
        {
+               .name = "bd71828-power",
+               .resources = bd71828_power_irqs,
+               .num_resources = ARRAY_SIZE(bd71828_power_irqs),
+       }, {
                .name = "bd71828-rtc",
                .resources = bd71828_rtc_irqs,
                .num_resources = ARRAY_SIZE(bd71828_rtc_irqs),

diff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h
index ce786c96404a3dc9d5124ffbbd507df89ca0e5ba..73a71ef6915254db920e4d63a3354ecfdac70f30 100644 (file)
--- a/include/linux/mfd/rohm-bd71828.h
+++ b/include/linux/mfd/rohm-bd71828.h
@@ -189,6 +189,69 @@ enum {
 /* Charger/Battey */
 #define BD71828_REG_CHG_STATE          0x65
 #define BD71828_REG_CHG_FULL           0xd2
+#define BD71828_REG_CHG_EN             0x6F
+#define BD71828_REG_DCIN_STAT          0x68
+#define BD71828_MASK_DCIN_DET          0x01
+#define BD71828_REG_VDCIN_U            0x9c
+#define BD71828_MASK_CHG_EN            0x01
+#define BD71828_CHG_MASK_DCIN_U                0x0f
+#define BD71828_REG_BAT_STAT           0x67
+#define BD71828_REG_BAT_TEMP           0x6c
+#define BD71828_MASK_BAT_TEMP          0x07
+#define BD71828_BAT_TEMP_OPEN          0x07
+#define BD71828_MASK_BAT_DET           0x20
+#define BD71828_MASK_BAT_DET_DONE      0x10
+#define BD71828_REG_CHG_STATE          0x65
+#define BD71828_REG_VBAT_U             0x8c
+#define BD71828_MASK_VBAT_U            0x0f
+#define BD71828_REG_VBAT_REX_AVG_U     0x92
+
+#define BD71828_REG_OCV_PWRON_U                0x8A
+
+#define BD71828_REG_VBAT_MIN_AVG_U     0x8e
+#define BD71828_REG_VBAT_MIN_AVG_L     0x8f
+
+#define BD71828_REG_CC_CNT3            0xb5
+#define BD71828_REG_CC_CNT2            0xb6
+#define BD71828_REG_CC_CNT1            0xb7
+#define BD71828_REG_CC_CNT0            0xb8
+#define BD71828_REG_CC_CURCD_AVG_U     0xb2
+#define BD71828_MASK_CC_CURCD_AVG_U    0x3f
+#define BD71828_MASK_CC_CUR_DIR                0x80
+#define BD71828_REG_VM_BTMP_U          0xa1
+#define BD71828_REG_VM_BTMP_L          0xa2
+#define BD71828_MASK_VM_BTMP_U         0x0f
+#define BD71828_REG_COULOMB_CTRL       0xc4
+#define BD71828_REG_COULOMB_CTRL2      0xd2
+#define BD71828_MASK_REX_CC_CLR                0x01
+#define BD71828_MASK_FULL_CC_CLR       0x10
+#define BD71828_REG_CC_CNT_FULL3       0xbd
+#define BD71828_REG_CC_CNT_CHG3                0xc1
+
+#define BD71828_REG_VBAT_INITIAL1_U    0x86
+#define BD71828_REG_VBAT_INITIAL1_L    0x87
+
+#define BD71828_REG_VBAT_INITIAL2_U    0x88
+#define BD71828_REG_VBAT_INITIAL2_L    0x89
+
+#define BD71828_REG_IBAT_U             0xb0
+#define BD71828_REG_IBAT_L             0xb1
+
+#define BD71828_REG_IBAT_AVG_U         0xb2
+#define BD71828_REG_IBAT_AVG_L         0xb3
+
+#define BD71828_REG_VSYS_AVG_U         0x96
+#define BD71828_REG_VSYS_AVG_L         0x97
+#define BD71828_REG_VSYS_MIN_AVG_U     0x98
+#define BD71828_REG_VSYS_MIN_AVG_L     0x99
+#define BD71828_REG_CHG_SET1           0x75
+#define BD71828_REG_ALM_VBAT_LIMIT_U   0xaa
+#define BD71828_REG_BATCAP_MON_LIMIT_U 0xcc
+#define BD71828_REG_CONF               0x64
+
+#define BD71828_REG_DCIN_CLPS          0x71
+
+#define BD71828_REG_MEAS_CLEAR         0xaf
 
 /* LEDs */
 #define BD71828_REG_LED_CTRL           0x4A