drm/amd/display: Update some comments to improve the code readability

This commit updates some comments to be more precise and adds another
small comment to some other parts to improve the code readability.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5cd86cfd6f73c2fab4997a1cab0d2ef5c309fddf..9475dab39af505a18d0f586dcc75691015b2a46b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -309,12 +309,12 @@ struct dc_dcc_setting {
        unsigned int max_compressed_blk_size;
        unsigned int max_uncompressed_blk_size;
        bool independent_64b_blks;
-       //These bitfields to be used starting with DCN
+       //These bitfields to be used starting with DCN 3.0
        struct {
-               uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
-               uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
-               uint32_t dcc_256_128_128 : 1;           //available starting with DCN
-               uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
+               uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
+               uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN 3.0
+               uint32_t dcc_256_128_128 : 1;           //available starting with DCN 3.0
+               uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN 3.0 (the best compression case)
        } dcc_controls;
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index efa2adf4f83dd38840122b81b99c9f03a391eaea..8da3084d933f1206344d2e2dc44de901c5331115 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -147,7 +147,7 @@
        uint32_t DCN_CUR1_TTU_CNTL1;\
        uint32_t VMID_SETTINGS_0
 
-
+/*shared with dcn3.x*/
 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
        DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
        uint32_t FLIP_PARAMETERS_3;\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
index 35dd4bac242ab608524923b4e2515a82596f143f..cd2bfcc51276503db21c0b7e5d8567c53b16a2ae 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
@@ -77,6 +77,7 @@ static void hubp201_program_requestor(struct hubp *hubp,
                        MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
                        CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 
+       /* no need to program PTE */
        REG_SET_5(DCHUBP_REQ_SIZE_CONFIG, 0,
                CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
                MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
@@ -99,6 +100,10 @@ static void hubp201_setup(
                struct _vcs_dpi_display_rq_regs_st *rq_regs,
                struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 {
+       /*
+        * otg is locked when this func is called. Register are double buffered.
+        * disable the requestors is not needed
+        */
        hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
        hubp201_program_requestor(hubp, rq_regs);
        hubp201_program_deadline(hubp, dlg_attr, ttu_attr);