&pci_state_reg);
        if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
            !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
-               u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
-
-               if (chiprevid == CHIPREV_ID_5701_A0 ||
-                   chiprevid == CHIPREV_ID_5701_B0 ||
-                   chiprevid == CHIPREV_ID_5701_B2 ||
-                   chiprevid == CHIPREV_ID_5701_B5) {
+               if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5701_B2 ||
+                   tp->pci_chip_rev_id == CHIPREV_ID_5701_B5) {
                        void __iomem *sram_base;
 
                        /* Write some dummy words into the SRAM status block
 
 #define  MISC_HOST_CTRL_TAGGED_STATUS   0x00000200
 #define  MISC_HOST_CTRL_CHIPREV                 0xffff0000
 #define  MISC_HOST_CTRL_CHIPREV_SHIFT   16
-#define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
-        (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
-         MISC_HOST_CTRL_CHIPREV_SHIFT)
+
 #define  CHIPREV_ID_5700_A0             0x7000
 #define  CHIPREV_ID_5700_A1             0x7001
 #define  CHIPREV_ID_5700_B0             0x7100