Modifications for 1.1.5:
======================================================================
+* Patch by Kári Davíðsson, 2 Mar 2002:
+ - add network configuration for FLAGADM board
+ - fix UPM tables for FLAGADM board
+
+* For config without hush shell: fix limitation of "autoscript"
+ command to console buffer size (CFG_CBSIZE) - the script can now
+ have arbitrary length - it is run line by line, and execution will
+ stop if an error is encountered.
+ NOTE: empty lines in the script are ignored (i. e. they don't cause
+ any auto-repeat of the previous command).
+
* Patch by Stefan Roese, 1 Mar 2002:
- Added ORSG board
- crc32 command extended - optionally write CRC to memory
XXX - this list needs to get updated!
- XXX - when using the (yet undocumented) "autoscript"
- command, be aware that the length of your
- "script" file is limited by the console bugger
- size (defined by CFG_CBSIZE in your board
- config file) - at least if you are NOT using
- the HUSH shell.
-
- Watchdog:
CONFIG_WATCHDOG
If this variable is defined, it enables watchdog
const uint sdram_table[] =
{
/* single read (offset 0x00 in upm ram) */
- 0x1f07c004, 0xeeaee004, 0x11adc004, 0xefbba000,
- 0x1ff74447,
+ 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
+ 0x1ff74c47,
/* Precharge */
- 0x1FF74C05,
- _NOT_USED_,
+ 0x1FF74C05,
+ _NOT_USED_,
_NOT_USED_,
/* burst read (offset 0x08 in upm ram) */
- 0x1f07c004, 0xeeaee004, 0x00adc004, 0x00afc000,
- 0x00afc000, 0x01afc000, 0x0fbb8001, 0x1ff74447,
+ 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
+ 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* single write (offset 0x18 in upm ram) */
- 0x1f27c004, 0xeeaea000, 0x01b90004, 0x1ff74447,
+ 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
/* Load moderegister */
0x1FF74C34, /*Precharge*/
0xEFEA8C34, /*NOP*/
- 0x1FB54C35, /*Load moderegister*/
- _NOT_USED_,
+ 0x1FB54C35, /*Load moderegister*/
+ _NOT_USED_,
/* burst write (offset 0x20 in upm ram) */
- 0x1f07c004, 0xeeaea000, 0x00ad4000, 0x00afc000,
- 0x00afc000, 0x01bb8004, 0x1ff74447, _NOT_USED_,
+ 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
+ 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* refresh (offset 0x30 in upm ram) */
};
/* GPL5 driven every cycle */
-/* the display and the DSP */
+/* the display and the DSP */
const uint dsp_disp_table[] =
{
/* single read (offset 0x00 in upm ram) */
- 0xefffc00c, 0x0fffc004, 0x0fffd004, 0x0fffc000,
- 0x3fffe004, 0xffffdfff, _NOT_USED_, _NOT_USED_,
+ 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
+ 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
/* burst read (offset 0x08 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* single write (offset 0x18 in upm ram) */
- 0xefffc00c, 0x0fffc004, 0x0fffd004, 0x0fffc000,
- 0x3fffe004, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
+ 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
/* burst write (offset 0x20 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* exception (offset 0x3C in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
};
int checkboard (void)
{
puts("FlagaDM V3.0 ");
- return 3; //Version 3
+ return 3; /*Version 3*/
}
long int initdram (int board_type)
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0;
- memctl->memc_or2 = CFG_OR2;
- memctl->memc_br2 = CFG_BR2;
+ memctl->memc_or2 = CFG_OR2;
+ memctl->memc_br2 = CFG_BR2;
udelay(100);
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
memctl->memc_mptpr = MPTPR_PTP_DIV16;
- memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X;
+ memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X;
/*Do the initialization of the SDRAM*/
/*Start with the precharge cycle*/
memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
- MCR_MLCF(1) | MCR_MAD(0x5));
+ MCR_MLCF(1) | MCR_MAD(0x5));
/*Then we need two refresh cycles*/
- memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X;
+ memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X;
memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
- MCR_MLCF(2) | MCR_MAD(0x30));
-
+ MCR_MLCF(2) | MCR_MAD(0x30));
+
/*Mode register programming*/
memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
- MCR_MLCF(1) | MCR_MAD(0x1C));
+ MCR_MLCF(1) | MCR_MAD(0x1C));
/* That should do it, just enable the periodic refresh in burst of 4*/
memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
- memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_B4DIS);
-
+ memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_B4DIS);
+
size_b0 = 16*1024*1024;
/*
memctl->memc_br1 = 0;
memctl->memc_br3 = 0;
- upmconfig(UPMB, (uint *)dsp_disp_table,
- sizeof(dsp_disp_table)/sizeof(uint));
+ upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
+
+ memctl->memc_mbmr = MAMR_GPL_B4DIS;
memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4;
return (size_b0);
}
-
extern image_header_t header; /* from cmd_bootm.c */
int
-autoscript(bd_t *bd, ulong addr)
+autoscript (bd_t *bd, ulong addr)
{
ulong crc, data, len;
image_header_t *hdr = &header;
memcpy (hdr, (char *)addr, sizeof(image_header_t));
if (hdr->ih_magic != IH_MAGIC) {
- printf("Bad magic number\n");
+ printf ("Bad magic number\n");
return 1;
}
crc = hdr->ih_hcrc;
hdr->ih_hcrc = 0;
- len = sizeof(image_header_t);
+ len = sizeof (image_header_t);
data = (ulong)hdr;
if (crc32(0, (char *)data, len) != crc) {
- printf("Bad header crc\n");
+ printf ("Bad header crc\n");
return 1;
}
data = addr + sizeof(image_header_t);
len = hdr->ih_size;
if (crc32(0, (char *)data, len) != hdr->ih_dcrc) {
- printf("Bad data crc\n");
+ printf ("Bad data crc\n");
return 1;
}
if (hdr->ih_type != IH_TYPE_SCRIPT) {
- printf("Bad image type\n");
+ printf ("Bad image type\n");
return 1;
}
- /* get len of script and make sure cmd is null terminated */
+ /* get length of script */
len_ptr = (ulong *)data;
- len = *len_ptr;
- if (len) {
- cmd = malloc (len + 1);
- if (!cmd)
- {
- return 1;
- }
- while (*len_ptr++);
- memcpy(cmd,(char *)len_ptr,len);
- *(cmd + len) = 0;
-#ifndef CFG_HUSH_PARSER
- /* also (for now) replace \n with ; */
- {
- int i;
-
- for (i=0; i<len; i++) {
- if (cmd[i] == '\n') {
- cmd[i] = ';';
+
+ if ((len = *len_ptr) == 0) {
+ printf ("Empty Script\n");
+ return 1;
+ }
+
+ if ((cmd = malloc (len + 1)) == NULL) {
+ return 1;
+ }
+
+ while (*len_ptr++);
+
+ /* make sure cmd is null terminated */
+ memcpy (cmd, (char *)len_ptr, len);
+ *(cmd + len) = 0;
+
+#ifdef CFG_HUSH_PARSER
+ rcode = parse_string_outer (cmd, FLAG_PARSE_SEMICOLON);
+#else
+ {
+ char *line = cmd;
+ char *next = cmd;
+
+ /*
+ * break into individual lines,
+ * and execute each line;
+ * terminate on error.
+ */
+ while (*next) {
+ if (*next == '\n') {
+ *next = '\0';
+ /* run only non-empty commands */
+ if ((next - line) > 1) {
+ if (run_command (line, bd, 0) < 0) {
+ rcode = 1;
+ break;
+ }
}
+ line = next + 1;
}
+ ++next;
}
-#endif
}
-#ifndef CFG_HUSH_PARSER
- rcode = run_command(cmd, bd, 0);
-#else
- rcode = parse_string_outer(cmd, FLAG_PARSE_SEMICOLON);
#endif
- free(cmd);
+ free (cmd);
return rcode;
}
if (argc < 2) {
addr = CFG_LOAD_ADDR;
} else {
- addr = simple_strtoul(argv[1],0,16);
+ addr = simple_strtoul (argv[1],0,16);
}
- printf("## Executing script at %08lx\n",addr);
- rcode = autoscript(bd,addr);
+ printf ("## Executing script at %08lx\n",addr);
+ rcode = autoscript (bd,addr);
return rcode;
}
#endif /* CFG_CMD_AUTOSCRIPT */
{
int rcode = 0;
#ifndef CFG_HUSH_PARSER
- if (run_command (getenv ("bootcmd"), bd, flag) == -1) rcode = 1;
+ if (run_command (getenv ("bootcmd"), bd, flag) < 0) rcode = 1;
#else
if (parse_string_outer(getenv("bootcmd"),
FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0 ) rcode = 1;
#endif /* CFG_CMD_BOOTD */
/* OK - call function to do the command */
- (cmdtp->cmd) (cmdtp, bd, flag, argc, argv);
+ if ((cmdtp->cmd) (cmdtp, bd, flag, argc, argv) != 0) {
+ return (-1);
+ }
repeatable &= cmdtp->repeatable;
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif /* CONFIG_BSEIP */
+/*** BSEIP **********************************************************/
+
+#ifdef CONFIG_FLAGADM
+/* Enet configuration for the FLAGADM */
+/* Enet on SCC2 */
+
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+#define PA_ENET_RXD ((ushort)0x0004)
+#define PA_ENET_TXD ((ushort)0x0008)
+#define PA_ENET_TCLK ((ushort)0x0100)
+#define PA_ENET_RCLK ((ushort)0x0400)
+#define PB_ENET_TENA ((uint)0x00002000)
+#define PC_ENET_CLSN ((ushort)0x0040)
+#define PC_ENET_RENA ((ushort)0x0080)
+
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00003400)
+#endif /* CONFIG_FLAGADM */
+
/*** C2MON **********************************************************/
#ifdef CONFIG_C2MON
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* (easy to change)
*/
-#undef DEBUG
-
-#define CONFIG_DELAYCACHEENABLE 1
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */
-#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/
+#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/
-#if 0
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
+#define CONFIG_8xx_CONS_SMC2 1
#undef CONFIG_8xx_CONS_NONE
-#else
-#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
-#define CONFIG_8xx_CONS_SMC2 1
-#undef CONFIG_8xx_CONS_NONE
-#endif
+
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#undef CONFIG_CLOCKS_IN_MHZ
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp"
+#if 0
+#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/ram ip=off panic=1;" \
- "bootm 40040000 400e0000"
-
-/* Björgvin */
-/* #define CONFIG_ETHADDR 0:1:2:3:4:A */
-/* Stephan */
-/* #define CONFIG_ETHADDR 0:1:2:3:4:9 */
-/* Kári */
-/* #define CONFIG_ETHADDR 0:1:2:3:4:5 */
+ "bootm 40040000 400e0000"
+#else
+#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1"
+#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000"
+#endif /* 0|1*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-/* #define CONFIG_WATCHDOG / * watchdog enabled */
+/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */
#undef CONFIG_WATCHDOG /* watchdog disabled */
-/* #define CONFIG_I2C 1 */
-/* #define CFG_I2C_SPEED 50000 */
-/* #define CFG_SOFT_I2C 1 */
-/* #define CFG_I2C_UCODE_PATCH 1 */
-/* #define CFG_I2C_DPMEM_OFFSET 0x1fc0 */
-
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \
CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
- CFG_CMD_ENV)
+ CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "EEG> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */
-#define CFG_LOAD_ADDR 0x40040000 /* default load address */
+#define CFG_LOAD_ADDR 0x40040000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
-#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_ENV_IS_IN_FLASH 1
-/* This is a litlebit wasteful, but one sector is 128kb and we have to
- * assigne a whole sector for the environment, so that we can safely
+#define CFG_ENV_IS_IN_FLASH 1
+/* This is a litlebit wasteful, but one sector is 128kb and we have to
+ * assigne a whole sector for the environment, so that we can safely
* erase and write it without disturbing the boot sector
*/
-#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
-#define CFG_SIUMCR ( SIUMCR_FRC | SIUMCR_DLK | SIUMCR_MLRC01 | SIUMCR_GB5E)
+#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
+ SIUMCR_MLRC01 | SIUMCR_GB5E)
+#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CFG_DER 0x2002000F*/
-#define CFG_DER 0
+#define CFG_DER 0
/*
* In the Flaga DM we have:
* untouched.
*/
-#define CFG_FLASH_PROTECTION 1
-/* #undef CFG_FLASH_PROTECTION */
+#define CFG_FLASH_PROTECTION 0
#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
-/*#define CFG_REMAP_OR_AM 0x80000000 / * OR addr mask */
#define CFG_OR_AM 0xff000000 /* OR addr mask */
#define CFG_OR_ATM 0x00006000
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \
OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
-/*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */
#define CFG_OR0_PRELIM (CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
*
*/
#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM ( 0x00000800 )
+#define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM)
#define CFG_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-#define CFG_OR2_PRELIM (CFG_OR_AM | CFG_OR_TIMING_SDRAM )
-/* #define CFG_BR2_PRELIM 0x00000081 */
-/* #define CFG_OR2_PRELIM (0xff000800 | OR_BI) */
+
#define CFG_BR2 CFG_BR2_PRELIM
#define CFG_OR2 CFG_OR2_PRELIM
/*
* MAMR settings for SDRAM
*/
-/* 0xd0802118 */
-#define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_TLFA_4X | MAMR_WLFA_1X | \
- MAMR_G0CLA_A11)
+#define CFG_MAMR_48_SDR (CFG_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \
+ | MAMR_G0CLA_A11)
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
-/* #define CFG_MAMR_PTA 0xd0000000 */
-#define CFG_MAMR_PTA 0xBB000000
-/* #define CFG_MAMR_PTA 0x0b000000 */
-/* #define CFG_MAMR_PTA 0x11000000 */
-
+#define CFG_MAMR_PTA 0x0F000000
/*
* BR4 and OR4 (DSP1)
*
*/
#define DSP_BASE 0x80000000
-
-#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI )
+
+#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
-
-/*
- * MBMR settings for DSP and DISPLAY
- *
- */
-/* #define CFG_MBMR_DSP ( MAMR_GPL_B4DIS ) */
/*
* Internal Definitions
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */
projects / users / rw / ppcboot.git / commitdiff