}
                val = tr32(VCPU_CFGSHDW);
                if (val & VCPU_CFGSHDW_ASPM_DBNC)
 -                      tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
 +                      tg3_flag_set(tp, ASPM_WORKAROUND);
                if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
-                   (val & VCPU_CFGSHDW_WOL_MAGPKT))
+                   (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
 -                      tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
 +                      tg3_flag_set(tp, WOL_ENABLE);
+                       device_set_wakeup_enable(&tp->pdev->dev, true);
+               }
                goto done;
        }
  
  
                if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
                    !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
 -                      tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
 +                      tg3_flag_clear(tp, WOL_CAP);
  
 -              if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
 +              if (tg3_flag(tp, WOL_CAP) &&
-                   (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
+                   (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
 -                      tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
 +                      tg3_flag_set(tp, WOL_ENABLE);
+                       device_set_wakeup_enable(&tp->pdev->dev, true);
+               }
  
                if (cfg2 & (1 << 17))
                        tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;