clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents

On the QCS404 platform the driver for the Global Clock Controller
doens't define gpll0_out_aux and gpll4_out_aux clocks, so it's not
possible to use them as parents. Remove entries for these clocks.

Note: backporting this patch to earlier kernels would also require a
previous patch which switches the gcc driver to use ARRAY_SIZE for
parent data arrays.

Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221226042154.2666748-6-dmitry.baryshkov@linaro.org

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index f60a0ab42da1a42798717e59fcbebb336d243af2..507c42d7f753f8d5d4e428b355097ec62c6873b9 100644 (file)
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -25,11 +25,9 @@ enum {
        P_CORE_BI_PLL_TEST_SE,
        P_DSI0_PHY_PLL_OUT_BYTECLK,
        P_DSI0_PHY_PLL_OUT_DSICLK,
-       P_GPLL0_OUT_AUX,
        P_GPLL0_OUT_MAIN,
        P_GPLL1_OUT_MAIN,
        P_GPLL3_OUT_MAIN,
-       P_GPLL4_OUT_AUX,
        P_GPLL4_OUT_MAIN,
        P_GPLL6_OUT_AUX,
        P_HDMI_PHY_PLL_CLK,
@@ -109,28 +107,24 @@ static const char * const gcc_parent_names_4[] = {
 static const struct parent_map gcc_parent_map_5[] = {
        { P_XO, 0 },
        { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
-       { P_GPLL0_OUT_AUX, 2 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const gcc_parent_names_5[] = {
        "cxo",
        "dsi0pll_byteclk_src",
-       "gpll0_out_aux",
        "core_bi_pll_test_se",
 };
 
 static const struct parent_map gcc_parent_map_6[] = {
        { P_XO, 0 },
        { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
-       { P_GPLL0_OUT_AUX, 3 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const gcc_parent_names_6[] = {
        "cxo",
        "dsi0_phy_pll_out_byteclk",
-       "gpll0_out_aux",
        "core_bi_pll_test_se",
 };
 
@@ -139,7 +133,6 @@ static const struct parent_map gcc_parent_map_7[] = {
        { P_GPLL0_OUT_MAIN, 1 },
        { P_GPLL3_OUT_MAIN, 2 },
        { P_GPLL6_OUT_AUX, 3 },
-       { P_GPLL4_OUT_AUX, 4 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
@@ -148,7 +141,6 @@ static const char * const gcc_parent_names_7[] = {
        "gpll0_out_main",
        "gpll3_out_main",
        "gpll6_out_aux",
-       "gpll4_out_aux",
        "core_bi_pll_test_se",
 };
 
@@ -207,14 +199,12 @@ static const char * const gcc_parent_names_11[] = {
 static const struct parent_map gcc_parent_map_12[] = {
        { P_XO, 0 },
        { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
-       { P_GPLL0_OUT_AUX, 2 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const gcc_parent_names_12[] = {
        "cxo",
        "dsi0pll_pclk_src",
-       "gpll0_out_aux",
        "core_bi_pll_test_se",
 };
 
@@ -237,40 +227,34 @@ static const char * const gcc_parent_names_13[] = {
 static const struct parent_map gcc_parent_map_14[] = {
        { P_XO, 0 },
        { P_GPLL0_OUT_MAIN, 1 },
-       { P_GPLL4_OUT_AUX, 2 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const gcc_parent_names_14[] = {
        "cxo",
        "gpll0_out_main",
-       "gpll4_out_aux",
        "core_bi_pll_test_se",
 };
 
 static const struct parent_map gcc_parent_map_15[] = {
        { P_XO, 0 },
-       { P_GPLL0_OUT_AUX, 2 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const gcc_parent_names_15[] = {
        "cxo",
-       "gpll0_out_aux",
        "core_bi_pll_test_se",
 };
 
 static const struct parent_map gcc_parent_map_16[] = {
        { P_XO, 0 },
        { P_GPLL0_OUT_MAIN, 1 },
-       { P_GPLL0_OUT_AUX, 2 },
        { P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const gcc_parent_names_16[] = {
        "cxo",
        "gpll0_out_main",
-       "gpll0_out_aux",
        "core_bi_pll_test_se",
 };