intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
                intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
                                        mode, adjusted_mode);
-               /*
-                * the mode->clock is used to calculate the Data&Link M/N
-                * of the pipe. For the eDP the fixed clock should be used.
-                */
-               mode->clock = intel_dp->panel_fixed_mode->clock;
        }
 
        if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 
        DRM_DEBUG_KMS("DP link computation with max lane count %i "
                      "max bw %02x pixel clock %iKHz\n",
-                     max_lane_count, bws[max_clock], mode->clock);
+                     max_lane_count, bws[max_clock], adjusted_mode->clock);
 
-       if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
+       if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode))
                return false;
 
        bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
-       mode_rate = intel_dp_link_required(mode->clock, bpp);
+       mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 
        for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
                for (clock = 0; clock <= max_clock; clock++) {