wifi: rtw89: 8922a: support different SAR configs by antenna

Set SAR configs to the corresponding CRs (control registers) according to
RF path. Then, declare to support SAR by antenna in chip info.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20250326020643.14487-11-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 6ef546d1b57557d3313445add3ddb79e858aacb4..d0840ad95e56cb646e0841ea9fd96cfa57924d06 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -9368,6 +9368,9 @@
 #define R_TSSI_PWR_P0 0xE610
 #define R_TSSI_PWR_P1 0xE710
 #define B_TSSI_CONT_EN BIT(3)
+#define R_P0_TXPWRB_BE 0xE61C
+#define R_P1_TXPWRB_BE 0xE71C
+#define B_TXPWRB_MAX_BE GENMASK(20, 12)
 #define R_TSSI_MAP_OFST_P0 0xE620
 #define R_TSSI_MAP_OFST_P1 0xE720
 #define B_TSSI_MAP_OFST_OFDM GENMASK(17, 9)

diff --git a/drivers/net/wireless/realtek/rtw89/rtw8922a.c b/drivers/net/wireless/realtek/rtw89/rtw8922a.c
index 5b45c18fbbf6de7c6f20b2d66b324f43285f79c5..cc595cae53f55585b621c2f40db9088535347d42 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/rtw8922a.c
+++ b/drivers/net/wireless/realtek/rtw89/rtw8922a.c
@@ -12,6 +12,7 @@
 #include "reg.h"
 #include "rtw8922a.h"
 #include "rtw8922a_rfk.h"
+#include "sar.h"
 #include "util.h"
 
 #define RTW8922A_FW_FORMAT_MAX 3
@@ -2233,6 +2234,31 @@ static void rtw8922a_set_tx_shape(struct rtw89_dev *rtwdev,
                rtw8922a_bb_tx_triangular(rtwdev, true, phy_idx);
 }
 
+static void rtw8922a_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
+                                       const struct rtw89_chan *chan,
+                                       enum rtw89_phy_idx phy_idx)
+{
+       struct rtw89_sar_parm sar_parm = {
+               .center_freq = chan->freq,
+               .force_path = true,
+       };
+       s16 sar_rf;
+       s8 sar_mac;
+
+       if (phy_idx != RTW89_PHY_0)
+               return;
+
+       sar_parm.path = RF_PATH_A;
+       sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
+       sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
+       rtw89_phy_write32_mask(rtwdev, R_P0_TXPWRB_BE, B_TXPWRB_MAX_BE, sar_rf);
+
+       sar_parm.path = RF_PATH_B;
+       sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
+       sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
+       rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB_BE, B_TXPWRB_MAX_BE, sar_rf);
+}
+
 static void rtw8922a_set_txpwr(struct rtw89_dev *rtwdev,
                               const struct rtw89_chan *chan,
                               enum rtw89_phy_idx phy_idx)
@@ -2244,6 +2270,7 @@ static void rtw8922a_set_txpwr(struct rtw89_dev *rtwdev,
        rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
        rtw8922a_set_txpwr_diff(rtwdev, chan, phy_idx);
        rtw8922a_set_txpwr_ref(rtwdev, phy_idx);
+       rtw8922a_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
 }
 
 static void rtw8922a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
@@ -2823,7 +2850,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
        .support_unii4          = true,
        .support_ant_gain       = true,
        .support_tas            = false,
-       .support_sar_by_ant     = false,
+       .support_sar_by_ant     = true,
        .ul_tb_waveform_ctrl    = false,
        .ul_tb_pwr_diff         = false,
        .rx_freq_frome_ie       = false,