return read_sysreg(pmceid1_el0);
 }
 
+static inline bool pmuv3_implemented(int pmuver)
+{
+       return !(pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||
+                pmuver == ID_AA64DFR0_EL1_PMUVer_NI);
+}
+
+static inline bool is_pmuv3p4(int pmuver)
+{
+       return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4;
+}
+
+static inline bool is_pmuv3p5(int pmuver)
+{
+       return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5;
+}
+
 #endif
 
  */
 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
 {
-       return (cpu_pmu->pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5);
+       return (is_pmuv3p5(cpu_pmu->pmuver));
 }
 
 static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
        int pmuver;
 
        pmuver = read_pmuver();
-       if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||
-           pmuver == ID_AA64DFR0_EL1_PMUVer_NI)
+       if (!pmuv3_implemented(pmuver))
                return;
 
        cpu_pmu->pmuver = pmuver;
                             pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 
        /* store PMMIR register for sysfs */
-       if (pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4 && (pmceid_raw[1] & BIT(31)))
+       if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31)))
                cpu_pmu->reg_pmmir = read_pmmir();
        else
                cpu_pmu->reg_pmmir = 0;