coresight: document the bindings for the ATCLK

Put in a blurb in the device tree bindings indicating that
coresight blocks may have an optional ATCLK.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 88602b75418e841a66d568d59652707eeb41bb4a..8711c10654799b56d3b24ff916cdb0162df4d967 100644 (file)
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -21,11 +21,14 @@ its hardware characteristcs.
        * reg: physical base address and length of the register
          set(s) of the component.
 
-       * clocks: the clock associated to this component.
-
-       * clock-names: the name of the clock as referenced by the code.
-         Since we are using the AMBA framework, the name should be
-         "apb_pclk".
+       * clocks: the clocks associated to this component.
+
+       * clock-names: the name of the clocks referenced by the code.
+         Since we are using the AMBA framework, the name of the clock
+         providing the interconnect should be "apb_pclk", and some
+         coresight blocks also have an additional clock "atclk", which
+         clocks the core of that coresight component. The latter clock
+         is optional.
 
        * port or ports: The representation of the component's port
          layout using the generic DT graph presentation found in