]> www.infradead.org Git - users/hch/misc.git/commitdiff
x86/cpu: Rename and move CPU model entry for Diamond Rapids
authorTony Luck <tony.luck@intel.com>
Mon, 11 Aug 2025 21:33:45 +0000 (14:33 -0700)
committerIngo Molnar <mingo@kernel.org>
Wed, 17 Sep 2025 09:22:11 +0000 (11:22 +0200)
This model was added as INTEL_PANTHERCOVE_X (based on the name of the
core) with a comment that the platform name is Diamond Rapids. It was
also placed at the end of the file in a new section for family 19
processors.

This is different from previous naming as Andrew Cooper noted.
PeterZ agreed and posted a patch[1] to fix the name and move it in
sequence with other Xeon servers. But without a commit description or
sign-off the patch wasn't ever applied.

Patch updated to cover one additional use of the #define by turbostat
and to change the "Family 6" comment to also list 18 and 19 since new
models in these families are mixed in with family 6.

Originally-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Link: https://lore.kernel.org/all/20250214130205.GK14028@noisy.programming.kicks-ass.net/
arch/x86/include/asm/intel-family.h
drivers/platform/x86/intel/speed_select_if/isst_if_common.c
drivers/platform/x86/intel/tpmi_power_domains.c
tools/power/x86/turbostat/turbostat.c

index e345dbdf933eb42162a43b9605e7af761b372ccc..f32a0eca2ae56ad4dcbf5542521d06a705b7a03d 100644 (file)
@@ -51,7 +51,7 @@
 #define INTEL_PENTIUM_MMX              IFM(5, 0x04) /* P55C */
 #define INTEL_QUARK_X1000              IFM(5, 0x09) /* Quark X1000 SoC */
 
-/* Family 6 */
+/* Family 6, 18, 19 */
 #define INTEL_PENTIUM_PRO              IFM(6, 0x01)
 #define INTEL_PENTIUM_II_KLAMATH       IFM(6, 0x03)
 #define INTEL_PENTIUM_III_DESCHUTES    IFM(6, 0x05)
 #define INTEL_GRANITERAPIDS_X          IFM(6, 0xAD) /* Redwood Cove */
 #define INTEL_GRANITERAPIDS_D          IFM(6, 0xAE)
 
+#define INTEL_DIAMONDRAPIDS_X          IFM(19, 0x01) /* Panther Cove */
+
 #define INTEL_BARTLETTLAKE             IFM(6, 0xD7) /* Raptor Cove */
 
 /* "Hybrid" Processors (P-Core/E-Core) */
 #define INTEL_P4_PRESCOTT_2M           IFM(15, 0x04)
 #define INTEL_P4_CEDARMILL             IFM(15, 0x06) /* Also Xeon Dempsey */
 
-/* Family 19 */
-#define INTEL_PANTHERCOVE_X            IFM(19, 0x01) /* Diamond Rapids */
-
 /*
  * Intel CPU core types
  *
index 71e104a068e9e207dc8da250e5556d29117a2754..7449873c3d4068f4aaa7a069ed023559899628a8 100644 (file)
@@ -790,7 +790,7 @@ static const struct x86_cpu_id isst_cpu_ids[] = {
        X86_MATCH_VFM(INTEL_GRANITERAPIDS_X,    SST_HPM_SUPPORTED),
        X86_MATCH_VFM(INTEL_ICELAKE_D,          0),
        X86_MATCH_VFM(INTEL_ICELAKE_X,          0),
-       X86_MATCH_VFM(INTEL_PANTHERCOVE_X,      SST_HPM_SUPPORTED),
+       X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X,    SST_HPM_SUPPORTED),
        X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X,   0),
        X86_MATCH_VFM(INTEL_SKYLAKE_X,          SST_MBOX_SUPPORTED),
        {}
index 8641353b2e06176023b7821be3294ddb59f8c850..7d93119a4c30ccdbf451d49361a83ff3427fe727 100644 (file)
@@ -85,7 +85,7 @@ static const struct x86_cpu_id tpmi_cpu_ids[] = {
        X86_MATCH_VFM(INTEL_ATOM_CRESTMONT,     NULL),
        X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X,    NULL),
        X86_MATCH_VFM(INTEL_GRANITERAPIDS_D,    NULL),
-       X86_MATCH_VFM(INTEL_PANTHERCOVE_X,      NULL),
+       X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X,    NULL),
        {}
 };
 MODULE_DEVICE_TABLE(x86cpu, tpmi_cpu_ids);
index 72a280e7a9d594441d8fa49f1146eb21e063de2e..47eb2d4d13a554f404703fa3d9888b0392976a23 100644 (file)
@@ -1195,7 +1195,7 @@ static const struct platform_data turbostat_pdata[] = {
        { INTEL_EMERALDRAPIDS_X, &spr_features },
        { INTEL_GRANITERAPIDS_X, &spr_features },
        { INTEL_GRANITERAPIDS_D, &spr_features },
-       { INTEL_PANTHERCOVE_X, &dmr_features },
+       { INTEL_DIAMONDRAPIDS_X, &dmr_features },
        { INTEL_LAKEFIELD, &cnl_features },
        { INTEL_ALDERLAKE, &adl_features },
        { INTEL_ALDERLAKE_L, &adl_features },