* 2. power off the acp tiles
         * 3. check and enter ulv state
         */
-               if (adev->powerplay.pp_funcs &&
-                       adev->powerplay.pp_funcs->set_powergating_by_smu)
-                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
        }
        return 0;
 }
         * 2. turn on acp clock
         * 3. power on acp tiles
         */
-               if (adev->powerplay.pp_funcs->set_powergating_by_smu)
-                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
        }
        return 0;
 }
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        bool enable = (state == AMD_PG_STATE_GATE);
 
-       if (adev->powerplay.pp_funcs &&
-               adev->powerplay.pp_funcs->set_powergating_by_smu)
-               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
+       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
 
        return 0;
 }
 
 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
                                                       bool enable)
 {
-       if (((adev->asic_type == CHIP_POLARIS11) ||
+       if ((adev->asic_type == CHIP_POLARIS11) ||
            (adev->asic_type == CHIP_POLARIS12) ||
-           (adev->asic_type == CHIP_VEGAM)) &&
-           adev->powerplay.pp_funcs->set_powergating_by_smu)
+           (adev->asic_type == CHIP_VEGAM))
                /* Send msg to SMU via Powerplay */
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
 
 
                return;
 
        if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
-               if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
-                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
 
        }
 }