iio: dac: adi-axi-dac: fix wrong register bitfield

Fix ADI_DAC_R1_MODE of AXI_DAC_REG_CNTRL_2.

Both generic DAC and ad3552r DAC IPs docs are reporting
bit 5 for it.

Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
Fixes: 4e3949a192e4 ("iio: dac: add support for AXI DAC IP core")
Cc: stable@vger.kernel.org
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Reviewed-by: Nuno Sa <nuno.sa@analog.com>
Link: https://patch.msgid.link/20241008-wip-bl-ad3552r-axi-v0-iio-testing-v5-1-3d410944a63d@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c
index 0cb00f3bec0453e56e1317d12fef3573bcc4621a..b8b4171b80436bb9049cb859f2337c64ab8e84a9 100644 (file)
--- a/drivers/iio/dac/adi-axi-dac.c
+++ b/drivers/iio/dac/adi-axi-dac.c
@@ -46,7 +46,7 @@
 #define AXI_DAC_REG_CNTRL_1            0x0044
 #define   AXI_DAC_SYNC                 BIT(0)
 #define AXI_DAC_REG_CNTRL_2            0x0048
-#define          ADI_DAC_R1_MODE               BIT(4)
+#define          ADI_DAC_R1_MODE               BIT(5)
 #define AXI_DAC_DRP_STATUS             0x0074
 #define   AXI_DAC_DRP_LOCKED           BIT(17)
 /* DAC Channel controls */