{
        struct mips3264_watch_reg_state *watches =
                ¤t->thread.watch.mips3264;
+       unsigned int watchhi_mask = MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW;
+
        switch (current_cpu_data.watch_reg_use_cnt) {
        default:
                BUG();
        case 4:
-               watches->watchhi[3] = (read_c0_watchhi3() &
-                                      (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+               watches->watchhi[3] = (read_c0_watchhi3() & watchhi_mask);
        case 3:
-               watches->watchhi[2] = (read_c0_watchhi2() &
-                                      (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+               watches->watchhi[2] = (read_c0_watchhi2() & watchhi_mask);
        case 2:
-               watches->watchhi[1] = (read_c0_watchhi1() &
-                                      (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+               watches->watchhi[1] = (read_c0_watchhi1() & watchhi_mask);
        case 1:
-               watches->watchhi[0] = (read_c0_watchhi0() &
-                                      (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
+               watches->watchhi[0] = (read_c0_watchhi0() & watchhi_mask);
        }
        if (current_cpu_data.watch_reg_use_cnt == 1 &&
            (watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) {