Modifications for 1.1.3:
======================================================================
+* Patch by Stefan Roese, 21 Dec 2001
+ - DU405 board added
+ - Minor changes to some ESD boards
+
* Patch by Josh Huber, 19 Dec 2001
- Renamed cpu/mpc74xx to cpu/74xx_7xx, added support for various
CPUs of those families.
LIST_4xx=" \
ADCIOP AR405 CANBT CPCI405 \
- CPCIISER4 CRAYL1 DASA_SIM ERIC \
- MIP405 OCRTC PIP405 W7OLMC \
- W7OLMG WALNUT405 \
+ CPCIISER4 CRAYL1 DASA_SIM DU405 \
+ ERIC MIP405 OCRTC PIP405 \
+ W7OLMC W7OLMG WALNUT405 \
"
#########################################################################
echo "VENDOR = esd" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+DU405_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd ./include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = du405" >>config.mk ; \
+ echo "CPU = ppc4xx" >>config.mk ; \
+ echo "VENDOR = esd" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
ERIC_config:unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
- int l_type;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
- if (!s || strncmp(s, "ADCIOP", 6)) {
- printf ("### No HW ID - assuming ADCIOP\n");
+ if (!i || strncmp(str, "ADCIOP", 6)) {
+ printf ("### No HW ID - assuming ADCIOP\n");
return (1);
}
- l_type = (*(s+6) == 'L');
+ puts(str);
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
putc ('\n');
- return (l_type);
+ return 1;
}
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
- int i;
int index;
int len;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
- if (!s || strncmp(s, "AR405", 5))
- {
- printf ("### No HW ID - assuming AR405");
- }
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
+ if (!i || strncmp(str, "AR405", 5)) {
+ printf ("### No HW ID - assuming AR405\n");
+ return (1);
+ }
+
+ puts(str);
- printf("\nFPGA: ");
+ puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
putc ('\n');
- return (0);
+ return 1;
}
/* ------------------------------------------------------------------------- */
/* set up serial port with default baudrate */
serial_init(0, CONFIG_BAUDRATE);
console_init_f();
-#endif
+#endif
/*
* Boot onboard FPGA
/* set up serial port with default baudrate */
serial_init(0, CONFIG_BAUDRATE);
console_init_f();
-#endif
+#endif
printf("\nFPGA: Booting failed ");
switch (status)
{
printf("FPGA: %s\n", &(fpgadata[index+1]));
index += len+3;
}
- putc ('\n');
+ putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--)
{
for (index=0;index<1000;index++)
udelay(1000);
}
- putc ('\n');
+ putc ('\n');
do_reset(NULL, NULL, 0, 0, NULL);
}
/*
* Setup port pins for normal operation
*/
- out32(IBM405GP_GPIO0_ODR, 0x00038000); /* no open drain pins */
- out32(IBM405GP_GPIO0_TCR, 0x07000100); /* setup for output */
- out32(IBM405GP_GPIO0_OR, 0x07038100); /* set output pins to high (default) */
+ out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(IBM405GP_GPIO0_TCR, 0x07038100); /* setup for output */
+ out32(IBM405GP_GPIO0_OR, 0x07030100); /* set output pins to high (default) */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
- int i;
int index;
int len;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
- if (!s || strncmp(s, "CANBT", 5))
- {
- printf ("### No HW ID - assuming CANBT");
- }
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
+ if (!i || strncmp(str, "CANBT", 5)) {
+ printf ("### No HW ID - assuming CANBT\n");
+ return (1);
+ }
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
+ puts(str);
- printf("\nFPGA: ");
+ puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
putc ('\n');
- return (0);
+ return 1;
}
/* ------------------------------------------------------------------------- */
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+ 0x01,0x01,0x13,0x02,0x09,0xe5,0xe6,0x02,0x01,0x02,0x06,0x37,0x0d,0x01,0x01,0x15,
+ 0x07,0xe6,0xe5,0xe5,0x04,0x03,0x05,0x47,0xe5,0xe5,0x0f,0x02,0xe5,0x07,0xe5,0x01,
+ 0x01,0xe5,0x01,0xe5,0x03,0x03,0xe5,0x38,0x0e,0x01,0xe5,0x2e,0x33,0x15,0xe5,0xe5,
+ 0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x02,0xe5,0xe6,
+ 0x07,0x01,0xe5,0x05,0x01,0xe6,0x04,0xe7,0x05,0x01,0x07,0x01,0x0b,0xe7,0x3d,0x15,
+ 0x21,0x03,0x03,0xe5,0x3e,0x38,0xe5,0xe5,0xe5,0x12,0x02,0x09,0x1e,0x07,0x32,0x03,
+ 0xe5,0x19,0x05,0x01,0x0a,0x09,0x06,0x3a,0xe5,0x01,0x23,0x03,0x17,0x3a,0x03,0xe5,
+ 0x1f,0x1d,0x16,0xe5,0x24,0xe5,0x1e,0x09,0x12,0x02,0x15,0x01,0x23,0xe7,0x3e,0x23,
+ 0x17,0x01,0xe5,0x3e,0x3c,0xe6,0x24,0x19,0x3d,0xe6,0x1b,0xe5,0x04,0x02,0xe5,0x08,
+ 0x38,0x12,0x33,0x36,0xe6,0x0b,0x01,0xe5,0xe5,0x6a,0x10,0xe6,0x02,0x0b,0xe5,0xe5,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x0b,0x03,0xe5,0x0f,0x09,0x09,0x09,0x09,0x04,0x04,0x01,0x09,0x09,0x09,
+ 0x01,0x07,0x0d,0xe5,0xe6,0x0e,0x09,0x03,0x05,0x09,0x09,0x04,0x06,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x09,0x0e,0x03,0x26,0x57,0x0f,0x09,0x09,0x09,0x09,0x0b,0x01,0x07,
+ 0x09,0x09,0x02,0x06,0x0e,0xe5,0xe6,0x0c,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0x03,0x03,0x09,0x09,
+ 0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x12,0xe6,0x0d,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0b,0x03,0x0e,0x09,0x09,0x09,0x09,0x03,
+ 0x07,0x09,0x09,0x09,0x09,0x0f,0x02,0xe5,0x79,0xe5,0x01,0x0e,0x09,0x09,0x09,0x09,
+ 0x08,0x02,0x09,0x09,0x09,0x09,0x11,0xe6,0x3e,0x3b,0x02,0x10,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x09,0x10,0xe5,0x7d,0x3f,0x3a,0xe5,0x01,0x3f,0x36,0x04,0x02,
+ 0x7a,0x01,0x01,0x13,0x3d,0x28,0x01,0x01,0x3f,0x33,0x0a,0x3f,0x34,0x08,0xe5,0x79,
+ 0x01,0x01,0x14,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0xe5,0x01,0x0f,
+ 0x09,0x09,0x09,0x09,0x07,0x03,0x09,0x09,0x09,0x08,0xe5,0x0d,0x03,0x3a,0x04,0x3a,
+ 0x02,0xe5,0x0c,0x09,0x03,0x05,0x09,0x09,0x03,0x07,0x09,0x09,0x07,0x01,0x1b,0x01,
+ 0xe5,0x0a,0x02,0x07,0x05,0x03,0x01,0x03,0x03,0x01,0x03,0x03,0x09,0x06,0xe5,0x02,
+ 0x04,0x04,0x04,0x02,0x06,0xe5,0x02,0x02,0x06,0x02,0xe5,0x02,0x03,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,
//-----------------------------------------------------------------------
addi r4,0,pb3ap
mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x04c0 // disable Ready, BEM=1
+// addis r4,0,0x0100
+// ori r4,r4,0x04c0 // disable Ready, BEM=1
+ addis r4,0,0x8000
+ ori r4,r4,0x0040 // disable Ready, BEM=1
mtdcr ebccfgd,r4
addi r4,0,pb3cr
mtdcr ebccfga,r4
addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
+// ori r4,r4,0xA000 // BW=0x1(16 bits)
+ ori r4,r4,0xC000 // BW=0x1(32 bits)
mtdcr ebccfgd,r4
nop // pass2 DCR errata #8
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
+ short n;
/* set up sector start address table */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n");
break;
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
+ short n;
CFG_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
-#if 0 /* enable when device IDs are available */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#endif
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x00800000; break; /* => 8 MB */
+
case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
info->sector_count = 16;
}
/* set up sector start address table */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
- int i;
int index;
int len;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
- if (!s)
- {
- printf ("### No HW ID - assuming CPCI405");
- }
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
+ if (!i) {
+ printf ("### No HW ID - assuming CPCI405");
+ }
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
+ puts(str);
if (ctermm2())
printf(" (CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
else
printf(" (PCI Adapter Version)");
- printf("\nFPGA: ");
+ puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
putc ('\n');
- return (0);
+ return 1;
}
/* ------------------------------------------------------------------------- */
int i;
uint pbcr;
unsigned long base_b0, base_b1;
+ int size_val;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
- pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+ switch (size_b1)
+ {
+ case 1<<20:
+ size_val = 0; break;
+ case 2<<20:
+ size_val = 1; break;
+ case 4<<20:
+ size_val = 2; break;
+ case 8<<20:
+ size_val = 3; break;
+ case 16<<20:
+ size_val = 4; break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val<<17);
mtdcr(ebccfgd, pbcr);
// printf("pb1cr = %x\n", pbcr);
}
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+ switch (size_b1)
+ {
+ case 1<<20:
+ size_val = 0; break;
+ case 2<<20:
+ size_val = 1; break;
+ case 4<<20:
+ size_val = 2; break;
+ case 8<<20:
+ size_val = 3; break;
+ case 16<<20:
+ size_val = 4; break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val<<17);
mtdcr(ebccfgd, pbcr);
// printf("pb0cr = %x\n", pbcr);
}
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
- int i;
int index;
int len;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
- if (!s || strncmp(s, "CPCIISER4", 9))
- {
- printf ("### No HW ID - assuming CPCIISER4");
- }
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
-
- for ( ; s<e; ++s) {
- putc (*s);
- }
- }
+ if (!i || strncmp(str, "CPCIISER4", 9)) {
+ printf ("### No HW ID - assuming CPCIISER4\n");
+ return (1);
+ }
+
+ puts(str);
- printf("\nFPGA: ");
+ puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
putc ('\n');
- return (0);
+ return 1;
}
/* ------------------------------------------------------------------------- */
int checkboard (void)
{
- unsigned char *s = getenv("serial#");
- unsigned char *e;
- int index, len, i;
- unsigned short val;
- int fpga;
-
- /*
- * Boot onboard FPGA
- */
- fpga = fpgaBoot();
-
- if (!s)
- {
- printf ("### No HW ID - assuming DASA_SIM");
+ int index;
+ int len;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
+ int fpga;
+ unsigned short val;
+
+ /*
+ * Boot onboard FPGA
+ */
+ fpga = fpgaBoot();
+
+ if (!i || strncmp(str, "DASA_SIM", 8)) {
+ printf ("### No HW ID - assuming DASA_SIM");
}
- else
- {
- for (e=s; *e; ++e) {
- if (*e == ' ')
- break;
- }
- for ( ; s<e; ++s) {
- putc (*s);
+ puts(str);
+
+ if (fpga == 0)
+ {
+ val = *(unsigned short *)0x30000202;
+ printf(" (Id=%d Version=%d Revision=%d)",
+ (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
+
+ printf("\nFPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++)
+ {
+ len = fpgadata[index];
+ printf("%s ", &(fpgadata[index+1]));
+ index += len+3;
+ }
+ }
+ else
+ {
+ printf("\nFPGA: Booting failed!");
}
- }
-
- if (fpga == 0)
- {
- val = *(unsigned short *)0x30000202;
- printf(" (Id=%d Version=%d Revision=%d)",
- (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
-
- printf("\nFPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++)
- {
- len = fpgadata[index];
- printf("%s ", &(fpgadata[index+1]));
- index += len+3;
- }
- }
- else
- {
- printf("\nFPGA: Booting failed!");
- }
- putc ('\n');
+ putc ('\n');
- return (0);
+ return 1;
}
--- /dev/null
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CPCIISER4 boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFD0000
+#TEXT_BASE = 0xFFFC0000
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include "du405.h"
+#include <asm/processor.h>
+#include <ppc4xx.h>
+#include <405gp_i2c.h>
+#include <command.h>
+#include <cmd_boot.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_pre_init (void)
+{
+ int index, len, i;
+ int status;
+
+#ifdef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ serial_init(0, CONFIG_BAUDRATE);
+ console_init_f();
+#endif
+
+ /*
+ * Boot onboard FPGA
+ */
+ status = fpga_boot_compressed();
+ if (status != 0)
+ {
+ /* booting FPGA failed */
+#ifndef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ serial_init(0, CONFIG_BAUDRATE);
+ console_init_f();
+#endif
+ printf("\nFPGA: Booting failed ");
+ switch (status)
+ {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++)
+ {
+ len = fpgadata[index];
+ printf("FPGA: %s\n", &(fpgadata[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--)
+ {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, NULL, 0, 0, NULL);
+ }
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
+ * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
+ * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicpr, 0xFFFFFFB1); /* set int polarities */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 100 us
+ */
+ mtebc(epcr, 0xb8400000);
+
+ return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ int index;
+ int len;
+ unsigned char str[64];
+ int i = getenv_r ("serial#", str, sizeof(str));
+
+ if (!i || strncmp(str, "DU405", 5)) {
+ printf ("### No HW ID - assuming DU405\n");
+ return (1);
+ }
+
+ puts(str);
+
+ puts("\nFPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++)
+ {
+ len = fpgadata[index];
+ printf("%s ", &(fpgadata[index+1]));
+ index += len+3;
+ }
+
+ putc ('\n');
+
+ /*
+ * Reset external DUART via FPGA
+ */
+ *(volatile unsigned char *)FPGA_MODE_REG = 0xff; /* reset high active */
+ *(volatile unsigned char *)FPGA_MODE_REG = 0x00; /* low again */
+
+ return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ return (16 * 1024*1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+ /* TODO: XXX XXX XXX */
+ printf ("test: 16 MB - ok\n");
+
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1)
+ {
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b1 = -size_b1;
+ pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+ mtdcr(ebccfgd, pbcr);
+ // printf("pb1cr = %x\n", pbcr);
+ }
+
+ if (size_b0)
+ {
+ mtdcr(ebccfga, pb1cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb1cr);
+ base_b0 = base_b1 - size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+ mtdcr(ebccfgd, pbcr);
+ // printf("pb0cr = %x\n", pbcr);
+ }
+
+ size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]);
+
+ flash_get_offsets (base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ base_b0+size_b0-CFG_MONITOR_LEN,
+ base_b0+size_b0-1,
+ &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]);
+
+ flash_get_offsets (base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ base_b1+size_b1-CFG_MONITOR_LEN,
+ base_b1+size_b1-1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0+size_b0-CFG_MONITOR_LEN,
+ base_b0+size_b0-1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
--- /dev/null
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+ 0x01,0x01,0x05,0x01,0x0a,0xe6,0xe5,0x07,0x4f,0x14,0x22,0x27,0x25,0xe6,0xe6,0x3b,
+ 0x13,0x8b,0x02,0x01,0x62,0x0e,0x11,0x59,0x02,0x01,0xe5,0x07,0x0a,0x0b,0x14,0x2b,
+ 0x0f,0x1f,0x4b,0xe5,0x01,0xe5,0x14,0x05,0x1b,0x23,0x15,0xe5,0x1f,0x4a,0xe6,0xe6,
+ 0x16,0xe5,0x08,0x13,0x09,0x08,0xe5,0x11,0xe5,0x0d,0x01,0xe5,0x2b,0x26,0x1b,0xe5,
+ 0x0c,0x09,0x09,0x01,0x07,0x01,0x07,0xe6,0x06,0x09,0x02,0x09,0x06,0x01,0xe5,0x08,
+ 0x02,0x03,0x04,0x3b,0x10,0xe5,0x19,0xe7,0x0c,0x09,0x0c,0x1c,0xe5,0x07,0x23,0x01,
+ 0x53,0x19,0xe5,0xe5,0x09,0x1b,0x4a,0x6c,0x02,0xe5,0x70,0x0f,0x60,0x0f,0x2f,0x01,
+ 0x07,0x01,0x03,0x09,0x01,0x07,0x09,0x74,0x0e,0xe5,0x10,0x01,0x1d,0x09,0x83,0x0e,
+ 0xe8,0x0d,0x03,0x2d,0x09,0x36,0x4d,0x0e,0x01,0xe6,0x02,0x0b,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x04,0x02,0xe5,0x03,0xe5,0x01,0xe6,0x06,0xe5,0x07,0xe5,0x08,0x08,
+ 0xe5,0x06,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0xe6,0x01,0x1a,0x09,0x04,0x04,0x09,0x02,0x06,
+ 0x09,0x09,0x13,0x01,0xe5,0x07,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,
+ 0xe5,0xe6,0x09,0x0e,0xe5,0xe7,0x04,0x06,0xe6,0x08,0x08,0x01,0x01,0x04,0x02,0x08,
+ 0x02,0x05,0x0a,0x0b,0x09,0x09,0x09,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x0e,0xe5,
+ 0x01,0x12,0x08,0x0a,0x09,0x09,0x0a,0x16,0x83,0x01,0x0f,0x04,0x04,0x09,0x06,0x01,
+ 0xe5,0x08,0x09,0x08,0xe5,0x08,0x09,0x01,0x07,0x02,0x08,0x09,0x01,0x07,0x09,0x09,
+ 0x05,0x03,0x09,0x09,0x09,0x09,0x0e,0xe6,0xe5,0x07,0x04,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x08,0x08,0xe5,0x08,0x08,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x0e,0x01,0xe6,0x02,0x09,0x02,0x06,0x01,0x07,0x01,0x01,0x0d,0x01,0x0b,
+ 0x09,0x07,0x0b,0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x10,0xe5,
+ 0xe6,0x0d,0x09,0x09,0x0a,0x01,0x06,0xe5,0xe5,0x19,0xe5,0xe5,0x0f,0xe5,0xe5,0x07,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0e,0xe5,0x0d,
+ 0x09,0x09,0x08,0x0a,0x08,0x05,0x03,0x05,0x04,0x08,0x0a,0x0b,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x11,0x01,0x0f,0x0a,0x08,0x1d,0x09,0x0c,0x13,0x71,0xe5,
+ 0x01,0x0e,0x06,0x02,0x09,0x09,0x09,0x09,0x13,0x13,0x08,0x02,0x05,0x03,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe6,0x0b,0x0d,0x10,0xe5,0x10,0x13,0x0a,
+ 0xe5,0x0f,0x01,0x6c,0x03,0x10,0x09,0x03,0x05,0x09,0x09,0x09,0x01,0x07,0x01,0x03,
+ 0x03,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x10,0xe5,0x3e,
+ 0x09,0x25,0x6f,0x02,0x3e,0x08,0x29,0x6d,0x02,0x68,0x08,0x02,0x09,0x13,0x09,0x3d,
+ 0x06,0xe5,0x17,0x45,0x65,0x19,0xe5,0xe6,0x58,0x16,0x1c,0x09,0x13,0x09,0x09,0x1e,
+ 0xe5,0xe6,0x16,0x2f,0x15,0x13,0x65,0x06,0x01,0xe6,0x70,0x51,0x14,0x09,0x17,0x45,
+ 0x84,0x14,0x02,0xe5,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x04,0x09,0x0b,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x0a,0x01,0xe5,0x0d,0xe5,0x06,
+ 0xe6,0x07,0xe5,0x08,0x09,0x08,0xe5,0x07,0xe5,0x08,0x07,0xe6,0x08,0x07,0x03,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x07,0xe6,0x03,0x04,0x0e,0x02,0xe5,0x11,0x13,0x0d,
+ 0x09,0x32,0x6c,0xe5,0x01,0x15,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x05,0x03,0x01,
+ 0x0d,0x03,0x01,0x03,0x07,0x03,0x05,0x03,0x05,0x09,0x03,0x05,0x03,0x05,0x09,0x09,
+ 0x0b,0x09,0x0f,0xe7,0x0a,0x03,0x01,0x02,0x06,0xe5,0xe5,0x03,0x01,0x02,0x03,0x03,
+ 0x01,0x03,0x03,0x01,0x04,0x01,0xe5,0xe5,0x03,0x02,0x01,0x03,0x07,0x05,0x01,0x07,
+ 0x03,0x07,0x03,0x05,0x03,0x01,0x07,0x09,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x07,0x04,0x06,0xe5,0x01,0xe5,0x04,0xe5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,
--- /dev/null
+//------------------------------------------------------------------------------+
+//
+// This source code has been made available to you by IBM on an AS-IS
+// basis. Anyone receiving this source is licensed under IBM
+// copyrights to use it in any way he or she deems fit, including
+// copying it, modifying it, compiling it, and redistributing it either
+// with or without modifications. No license under IBM patents or
+// patent applications is to be implied by the copyright license.
+//
+// Any user of this software should understand that IBM cannot provide
+// technical support for this software and will not be responsible for
+// any consequences resulting from the use of this software.
+//
+// Any person who transfers this source code or any derivative work
+// must include the IBM copyright notice, this paragraph, and the
+// preceding two paragraphs in the transferred software.
+//
+// COPYRIGHT I B M CORPORATION 1995
+// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+//-------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Function: ext_bus_cntlr_init
+// Description: Initializes the External Bus Controller for the external
+// peripherals. IMPORTANT: For pass1 this code must run from
+// cache since you can not reliably change a peripheral banks
+// timing register (pbxap) while running code from that bank.
+// For ex., since we are running from ROM on bank 0, we can NOT
+// execute the code that modifies bank 0 timings from ROM, so
+// we run it from cache.
+// Bank 0 - Flash bank 0
+// Bank 1 - Flash bank 1
+// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400)
+// Bank 3 - IDE (CompactFlash)
+// Bank 4 - Quart
+// Bank 5 - not used
+// Bank 6 - not used
+// Bank 7 - not used
+//-----------------------------------------------------------------------------
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+//-----------------------------------------------------------------------------
+// Function: sdram_init
+// Description: Configures SDRAM memory banks.
+// Auto Memory Configuration option reads the SDRAM EEPROM
+// via the IIC bus and then configures the SDRAM memory
+// banks appropriately. If Auto Memory Configuration is
+// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
+// plugged, ie. the DIMM that shipped wih the Eval board.
+//-----------------------------------------------------------------------------
+ .globl sdram_init
+
+sdram_init:
+
+ mflr r31
+
+ //-------------------------------------------------------------------
+ // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
+ //-------------------------------------------------------------------
+ addi r4,0,mem_mb0cf
+ mtdcr memcfga,r4
+ addis r4,0,0x0004
+ ori r4,r4,0x6001
+ mtdcr memcfgd,r4
+
+ //-------------------------------------------------------------------
+ // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+ // To set the appropriate timings, we need to know the SDRAM speed.
+ // We can use the PLB speed since the SDRAM speed is the same as
+ // the PLB speed. The PLB speed is the FBK divider times the
+ // 405GP reference clock, which on the Walnut board is 33Mhz.
+ // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
+ // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
+ // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
+ // maybe 133Mhz.
+ //-------------------------------------------------------------------
+ mfdcr r5,strap // determine FBK divider
+ // via STRAP reg to calc PLB speed.
+ // SDRAM speed is the same as the PLB
+ // speed.
+ rlwinm r4,r5,4,0x3 // get FBK divide bits
+
+..chk_66:
+ cmpi %cr0,0,r4,0x1
+ bne ..chk_100
+ addis r6,0,0x0085 // SDTR1 value for 66Mhz
+ ori r6,r6,0x4005
+ addis r7,0,0x03F8 // RTR value for 66Mhz
+ b ..sdram_ok
+..chk_100:
+ cmpi %cr0,0,r4,0x2
+ bne ..chk_133
+ addis r6,0,0x0086 // SDTR1 value for 100Mhz
+ ori r6,r6,0x400D
+ addis r7,0,0x05F0 // RTR value for 100Mhz
+ b ..sdram_ok
+..chk_133:
+ addis r6,0,0x0107 // SDTR1 value for 133Mhz
+ ori r6,r6,0x4015
+ addis r7,0,0x07F0 // RTR value for 133Mhz
+
+..sdram_ok:
+ //-------------------------------------------------------------------
+ // Set SDTR1
+ //-------------------------------------------------------------------
+ addi r4,0,mem_sdtr1
+ mtdcr memcfga,r4
+ mtdcr memcfgd,r6
+
+ //-------------------------------------------------------------------
+ // Set RTR
+ //-------------------------------------------------------------------
+ addi r4,0,mem_rtr
+ mtdcr memcfga,r4
+ mtdcr memcfgd,r7
+
+ //-------------------------------------------------------------------
+ // Delay to ensure 200usec have elapsed since reset. Assume worst
+ // case that the core is running 200Mhz:
+ // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ //-------------------------------------------------------------------
+ addis r3,0,0x0000
+ ori r3,r3,0xA000 // ensure 200usec have passed since reset
+ mtctr r3
+..spinlp2:
+ bdnz ..spinlp2 // spin loop
+
+ //-------------------------------------------------------------------
+ // Set memory controller options reg, MCOPT1.
+ // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
+ // read/prefetch.
+ //-------------------------------------------------------------------
+ addi r4,0,mem_mcopt1
+ mtdcr memcfga,r4
+ addis r4,0,0x8080 // set DC_EN=1
+ ori r4,r4,0x0000
+ mtdcr memcfgd,r4
+
+ //-------------------------------------------------------------------
+ // Delay to ensure 10msec have elapsed since reset. This is
+ // required for the MPC952 to stabalize. Assume worst
+ // case that the core is running 200Mhz:
+ // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
+ // This delay should occur before accessing SDRAM.
+ //-------------------------------------------------------------------
+ addis r3,0,0x001E
+ ori r3,r3,0x8480 // ensure 10msec have passed since reset
+ mtctr r3
+..spinlp3:
+ bdnz ..spinlp3 // spin loop
+
+ mtlr r31 // restore lr
+ blr
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+ board/esd/du405/init.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/crc32.o (.text)
+ ppc/extable.o (.text)
+ ppc/zlib.o (.text)
+
+/* . = env_offset;*/
+/* common/environment.o(.text)*/
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/extable.o (.text)
+
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
#if defined(CONFIG_BOARD_PRE_INIT) || \
- defined(CONFIG_ADCIOP) || \
- defined(CONFIG_AR405) || \
- defined(CONFIG_CANBT) || \
- defined(CONFIG_CPCI405) || \
- defined(CONFIG_CPCIISER4) || \
defined(CONFIG_CU824) || \
- defined(CONFIG_DASA_SIM) || \
defined(CONFIG_EVB64260) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_MPC8260ADS)|| \
- defined(CONFIG_OCRTC) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_WALNUT405) || \
defined(CONFIG_W7O)
/*
* Use internal cpu clock to generate serial clock
*/
-#if 0
+#ifdef CFG_IGNORE_405_UART_ERRATA_59
/*
* The divisor bits are STUCK on ALL IBM 405GP/CR Rev. D silicon.
* RTF Errata!
mtdcr(cntrl0, cntrl0Reg); /* Divisor stuck at 31 */
br_reg = ( ( (cpu_clock / (16 * (((mfdcr(cntrl0) & 0x3e) >> 1) + 1)) * 10)
/ baudrate ) + 5 ) / 10;
-#endif /* 0 */
+#endif /* CFG_IGNORE_405_UART_ERRATA_59 */
#endif /* CFG_EXT_SERIAL_CLOCK */
br_reg = (((CFG_EXT_SERIAL_CLOCK*10)/16) / baudrate + 5) / 10;
#else
-#if 0
+#ifdef CFG_IGNORE_405_UART_ERRATA_59
/*
* The divisor bits are STUCK on ALL IBM 405GP/CR Rev. D silicon.
* RTF Errata!
#else
br_reg = ( ( (cpu_clock / (16 * (((mfdcr(cntrl0) & 0x3e) >> 1) + 1)) * 10)
/ baudrate ) + 5 ) / 10;
-#endif /* 0 */
+#endif /* CFG_IGNORE_405_UART_ERRATA_59 */
#endif
#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_CPUCLOCK 66
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_AR405 1 /* ...on a AR405 board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CANBT 1 /* ...on a CANBT board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
- "console=ttyS0,115200" \
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
"bootm ffe00000 ffe80000"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_I2C_X /* 8 bit access */
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x200 /* 512 bytes may be used for env vars */
+#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_CPUCLOCK 66
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_DU405 1 /* ...on a DU405 board */
+
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
+#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
+
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND "bootm fff00000"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_PCI | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_IDE | \
+ CFG_CMD_ELF | \
+ CFG_CMD_EEPROM )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */
+#define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_RESET /* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0xF0100000
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFFFD0000
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#undef CONFIG_I2C_X /* 8 bit access */
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
+ /* total size of a CAT24WC08 is 1024 bytes */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
+ /* 16 byte page write mode using*/
+ /* last 4 bits of the address */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
+#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
+#define CAN_BA 0xF0000000 /* CAN Base Address */
+#define DUART_BA 0xF0300000 /* DUART Base Address */
+#define CF_BA 0xF0100000 /* CompactFlash Base Address */
+#define SRAM_BA 0xF0200000 /* SRAM Base Address */
+#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
+#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
+
+#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization */
+#define CFG_EBC_PB1AP 0x92015480
+#define CFG_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0) initialization */
+#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (DUART) initialization */
+#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (CompactFlash IDE) initialization */
+#define CFG_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 5 (SRAM) initialization */
+#define CFG_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 6 (DURAG Bus IO Space) initialization */
+#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
+
+/* Memory Bank 7 (DURAG Bus Mem Space) initialization */
+#define CFG_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
+
+
+/* On Chip Memory location */
+#define OCM_DATA_ADDR 0xF8000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
+#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
+
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
+
+/*
+ * Macro for accessing the indirect EBC register
+ */
+#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+
+
#ifndef __ASSEMBLY__
typedef struct
defined(CONFIG_CPCIISER4) || \
defined(CONFIG_OCRTC) || \
defined(CONFIG_DASA_SIM) || \
+ defined(CONFIG_DU405) || \
defined(CONFIG_ERIC) || \
defined(CONFIG_MOUSSE) || \
defined(CONFIG_BAB750) || \
defined(CONFIG_CCM) || \
defined(CONFIG_CPCI405) || \
defined(CONFIG_CPCIISER4) || \
+ defined(CONFIG_DU405) || \
defined(CONFIG_HYMOD) || \
defined(CONFIG_IP860) || \
defined(CONFIG_LWMON) || \
projects / users / rw / ppcboot.git / commitdiff