if (priv->r8185) {
                reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
-               reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
-               reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
+               reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
+               reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
                rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
 
                reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
-               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
-               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
+               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
+               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
                reg |=  RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
                rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 
 
        rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
 
        reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
-       reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
+       reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
        rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
 
        /* Auto Rate Fallback Register (ARFR): 1M-54M setting */
                rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
 
                reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
-               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
-               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
+               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
+               reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
                reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
                rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 
        rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
 
        reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
-       reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
-       reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
+       reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
+       reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
        rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
 
        reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
-       reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
-       reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
+       reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
+       reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
        reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
        rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 
 
        __le32  HSSI_PARA;
        u8      reserved_13[4];
        u8      TX_AGC_CTL;
-#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT                (1 << 0)
-#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT      (1 << 1)
-#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT                        (1 << 2)
+#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN      (1 << 0)
+#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL    (1 << 1)
+#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT                (1 << 2)
        u8      TX_GAIN_CCK;
        u8      TX_GAIN_OFDM;
        u8      TX_ANTENNA;
        u8      SLOT;
        u8      reserved_16[5];
        u8      CW_CONF;
-#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT     (1 << 0)
-#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT  (1 << 1)
+#define RTL818X_CW_CONF_PERPACKET_CW   (1 << 0)
+#define RTL818X_CW_CONF_PERPACKET_RETRY        (1 << 1)
        u8      CW_VAL;
        u8      RATE_FALLBACK;
 #define RTL818X_RATE_FALLBACK_ENABLE   (1 << 7)