clk: renesas: r9a08g045: Add DMA clocks and resets

Add the missing DMA clock and resets.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240711123405.2966302-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index a891bfc3ab5a882699c46c39cd09c79a3f776091..213499fc8fb56485afcc6d8dd94bc8d81f0b9968 100644 (file)
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -193,6 +193,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
        DEF_MOD("ia55_pclk",            R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
        DEF_MOD("ia55_clk",             R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
        DEF_MOD("dmac_aclk",            R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
+       DEF_MOD("dmac_pclk",            R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1),
        DEF_MOD("wdt0_pclk",            R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0),
        DEF_MOD("wdt0_clk",             R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1),
        DEF_MOD("sdhi0_imclk",          R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
@@ -226,6 +227,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
        DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
        DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
        DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
+       DEF_RST(R9A08G045_DMAC_ARESETN, 0x82c, 0),
+       DEF_RST(R9A08G045_DMAC_RST_ASYNC, 0x82c, 1),
        DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0),
        DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
        DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),