drm/amd/display: Fix DCN35 set min dispclk logic

[Why]

Setting min dispclk to 50Mhz outside clock lowering function causes
unnecessary calls to SMU to lower dispclk and causes dentist hangs when
there is no stream on the pipes.

[How]

Move the set minimum dispclk logic inside the lowering dispclk if
statement.

Fixes: 234441320552 ("DCN35 set min dispclk to 50Mhz")
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Nicholas Susanto <Nicholas.Susanto@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index f50054089da744ff1c503a0cd6bda34f908b0cfa..97164b5585a84c348c464dd1ffe759863af1aea1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -305,9 +305,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
        if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
                new_clocks->ref_dtbclk_khz = 600000;
 
-       if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
-               new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
-
        /*
         * if it is safe to lower, but we are already in the lower state, we don't have to do anything
         * also if safe to lower is false, we just go in the higher state
@@ -385,6 +382,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
        if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
                dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
 
+               if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
+                       new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
+
                clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
                dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
                dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);