MIPS: Give Octeon+ CPUs their own cputype.

This allows us to treat them differently at runtime.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/951/
Patchwork: http://patchwork.linux-mips.org/patch/987/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index cf373a95fe4ad1e7ee1391f2dceeac41dba5ad2e..a5acda41694696f598c957e0a1d8124dfb7d40cf 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -224,7 +224,7 @@ enum cpu_type_enum {
         * MIPS64 class processors
         */
        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-       CPU_CAVIUM_OCTEON,
+       CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
 
        CPU_LAST
 };

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 9ea5ca89e85f75636e1c3280211131e893e2edc9..be5bb16be4e0a01df31ba41c21298367780eff97 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -162,6 +162,7 @@ void __init check_wait(void)
        case CPU_BCM6348:
        case CPU_BCM6358:
        case CPU_CAVIUM_OCTEON:
+       case CPU_CAVIUM_OCTEON_PLUS:
                cpu_wait = r4k_wait;
                break;
 
@@ -911,12 +912,16 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
        case PRID_IMP_CAVIUM_CN38XX:
        case PRID_IMP_CAVIUM_CN31XX:
        case PRID_IMP_CAVIUM_CN30XX:
+               c->cputype = CPU_CAVIUM_OCTEON;
+               __cpu_name[cpu] = "Cavium Octeon";
+               goto platform;
        case PRID_IMP_CAVIUM_CN58XX:
        case PRID_IMP_CAVIUM_CN56XX:
        case PRID_IMP_CAVIUM_CN50XX:
        case PRID_IMP_CAVIUM_CN52XX:
-               c->cputype = CPU_CAVIUM_OCTEON;
-               __cpu_name[cpu] = "Cavium Octeon";
+               c->cputype = CPU_CAVIUM_OCTEON_PLUS;
+               __cpu_name[cpu] = "Cavium Octeon+";
+platform:
                if (cpu == 0)
                        __elf_platform = "octeon";
                break;

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index af85959e59f5832b3c9154a1e1a27b03b2f3f149..0f9c488044d155aa0c9a7c262edfe6e1777d405e 100644 (file)
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void)
 
        switch (c->cputype) {
        case CPU_CAVIUM_OCTEON:
+       case CPU_CAVIUM_OCTEON_PLUS:
                config1 = read_c0_config1();
                c->icache.linesz = 2 << ((config1 >> 19) & 7);
                c->icache.sets = 64 << ((config1 >> 22) & 7);
@@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void)
                        c->icache.sets * c->icache.ways * c->icache.linesz;
                c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
                c->dcache.linesz = 128;
-               if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                       c->dcache.sets = 1; /* CN3XXX has one Dcache set */
-               else
+               if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
                        c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
+               else
+                       c->dcache.sets = 1; /* CN3XXX has one Dcache set */
                c->dcache.ways = 64;
                dcache_size =
                        c->dcache.sets * c->dcache.ways * c->dcache.linesz;