media: cadence: csi2rx: Soft reset the streams before starting capture

This resets the stream state machines and FIFOs, giving them a clean
slate. On J721E if the streams are not reset before starting the
capture, the captured frame gets wrapped around vertically on every run
after the first.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Tested-by: Julien Massot <julien.massot@collabora.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>

diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c
index 77e2413c345aa99f9b7ee7d26e0cb50bdbff5e95..913f84c341f4b5ff4a48348c955d898f0ff5376d 100644 (file)
--- a/drivers/media/platform/cadence/cdns-csi2rx.c
+++ b/drivers/media/platform/cadence/cdns-csi2rx.c
@@ -40,6 +40,7 @@
 #define CSI2RX_STREAM_BASE(n)          (((n) + 1) * 0x100)
 
 #define CSI2RX_STREAM_CTRL_REG(n)              (CSI2RX_STREAM_BASE(n) + 0x000)
+#define CSI2RX_STREAM_CTRL_SOFT_RST                    BIT(4)
 #define CSI2RX_STREAM_CTRL_START                       BIT(0)
 
 #define CSI2RX_STREAM_DATA_CFG_REG(n)          (CSI2RX_STREAM_BASE(n) + 0x008)
@@ -134,12 +135,23 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev)
 
 static void csi2rx_reset(struct csi2rx_priv *csi2rx)
 {
+       unsigned int i;
+
+       /* Reset module */
        writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT,
               csi2rx->base + CSI2RX_SOFT_RESET_REG);
+       /* Reset individual streams. */
+       for (i = 0; i < csi2rx->max_streams; i++) {
+               writel(CSI2RX_STREAM_CTRL_SOFT_RST,
+                      csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
+       }
 
-       udelay(10);
+       usleep_range(10, 20);
 
+       /* Clear resets */
        writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG);
+       for (i = 0; i < csi2rx->max_streams; i++)
+               writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
 }
 
 static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx)