if (DISPLAY_VER(i915) == 13) {
                for_each_dsi_port(port, intel_dsi->ports)
                        intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
-                                    TGL_DSI_CHKN_LSHS_GB, 0x4);
+                                    TGL_DSI_CHKN_LSHS_GB_MASK,
+                                    TGL_DSI_CHKN_LSHS_GB(4));
        }
 }
 
 
 #define TGL_DSI_CHKN_REG(port)         _MMIO_PORT(port,        \
                                                    _TGL_DSI_CHKN_REG_0, \
                                                    _TGL_DSI_CHKN_REG_1)
-#define TGL_DSI_CHKN_LSHS_GB                   REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB_MASK              REG_GENMASK(15, 12)
+#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)      REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
+                                                              (byte_clocks))
 
 /* Display Stream Splitter Control */
 #define DSS_CTL1                               _MMIO(0x67400)