temp &= ~(UCR1_RRDYEN);
                writel(temp, sport->port.membase + UCR1);
        }
-       /* Clear any pending ORE flag before enabling interrupt */
-       temp = readl(sport->port.membase + USR2);
-       writel(temp | USR2_ORE, sport->port.membase + USR2);
-
-       temp = readl(sport->port.membase + UCR4);
-       temp |= UCR4_OREN;
-       writel(temp, sport->port.membase + UCR4);
 
        if (!sport->dma_is_enabled) {
                temp = readl(sport->port.membase + UCR1);
 
        writel(temp, sport->port.membase + UCR1);
 
+       /* Clear any pending ORE flag before enabling interrupt */
+       temp = readl(sport->port.membase + USR2);
+       writel(temp | USR2_ORE, sport->port.membase + USR2);
+
+       temp = readl(sport->port.membase + UCR4);
+       temp |= UCR4_OREN;
+       writel(temp, sport->port.membase + UCR4);
+
        temp = readl(sport->port.membase + UCR2);
        temp |= (UCR2_RXEN | UCR2_TXEN);
        if (!sport->have_rtscts)