static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
                                        u32 aggrLen)
 {
+#define FIRST_DESC_NDELIMS 60
        struct ar9003_txc *ads = (struct ar9003_txc *) ds;
 
        ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
 
-       ads->ctl17 &= ~AR_AggrLen;
-       ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+       if (ah->ent_mode & AR_ENT_OTP_MPSD) {
+               u32 ctl17, ndelim;
+               /*
+                * Add delimiter when using RTS/CTS with aggregation
+                * and non enterprise AR9003 card
+                */
+               ctl17 = ads->ctl17;
+               ndelim = MS(ctl17, AR_PadDelim);
+
+               if (ndelim < FIRST_DESC_NDELIMS) {
+                       aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
+                       ndelim = FIRST_DESC_NDELIMS;
+               }
+
+               ctl17 &= ~AR_AggrLen;
+               ctl17 |= SM(aggrLen, AR_AggrLen);
+
+               ctl17 &= ~AR_PadDelim;
+               ctl17 |= SM(ndelim, AR_PadDelim);
+
+               ads->ctl17 = ctl17;
+       } else {
+               ads->ctl17 &= ~AR_AggrLen;
+               ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+       }
 }
 
 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
 
        if (AR_SREV_9300_20_OR_LATER(ah))
                pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
 
+       if (AR_SREV_9300_20_OR_LATER(ah))
+               ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
+
        if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
                pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
 
 
 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
 #define AR_ENT_OTP               0x40d8
 #define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
+#define AR_ENT_OTP_MPSD                0x00800000
 
 #define AR_RTC_9300_PLL_DIV          0x000003ff
 #define AR_RTC_9300_PLL_DIV_S        0