struct clk              *clk_io;
        struct clk              *clk_bus[MAX_BUS_CLK];
+       unsigned long           clk_rates[MAX_BUS_CLK];
 };
 
 /**
                return wanted - rate;
        }
 
-       rate = clk_get_rate(clksrc);
+       rate = ourhost->clk_rates[src];
 
        for (shift = 0; shift < 8; ++shift) {
                if ((rate >> shift) <= wanted)
                writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 
                ourhost->cur_clk = best_src;
-               host->max_clk = clk_get_rate(clk);
+               host->max_clk = ourhost->clk_rates[best_src];
 
                ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
                ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
                 */
                sc->cur_clk = ptr;
 
+               sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
+
                dev_info(dev, "clock source %d: %s (%ld Hz)\n",
-                        ptr, name, clk_get_rate(clk));
+                               ptr, name, sc->clk_rates[ptr]);
        }
 
        if (clks == 0) {