drm/i915/tc: Add an enum for the TypeC pin assignment

Add an enum for the TypeC pin assignment, which is a better way to pass
its value around than a plain integer. While at it add a description for
each pin assignment, based on the DP and DP Alt mode Standards, opting
for more details to ease any future debugging related to a given pin
assignment and the cables / sink types used.

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
[Imre: s/deined/defined in pin assignment enum documentation.]
Link: https://lore.kernel.org/r/20250805073700.642107-10-imre.deak@intel.com
Signed-off-by: Imre Deak <imre.deak@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 7bd09d981cd2d065b631043be26b11b8c478550c..9d71e26a4fa274475a38c7be38995a0ee29486b7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2890,6 +2890,7 @@ enum skl_power_gate {
 #define   DP_PIN_ASSIGNMENT_SHIFT(idx)         ((idx) * 4)
 #define   DP_PIN_ASSIGNMENT_MASK(idx)          (0xf << ((idx) * 4))
 #define   DP_PIN_ASSIGNMENT(idx, x)            ((x) << ((idx) * 4))
+/* See enum intel_tc_pin_assignment for the pin assignment field values. */
 
 #define _TCSS_DDI_STATUS_1                     0x161500
 #define _TCSS_DDI_STATUS_2                     0x161504
@@ -2897,6 +2898,7 @@ enum skl_power_gate {
                                                                 _TCSS_DDI_STATUS_1, \
                                                                 _TCSS_DDI_STATUS_2))
 #define  TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK   REG_GENMASK(28, 25)
+/* See enum intel_tc_pin_assignment for the pin assignment field values. */
 #define  TCSS_DDI_STATUS_READY                 REG_BIT(2)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT   REG_BIT(1)
 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT   REG_BIT(0)

diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 41bd82089180f608511ed8f82f91ed44764f84ce..ffead1cbf10f3ee2fc63b8b86716cb71840bb69a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -23,11 +23,6 @@
 #include "intel_modeset_lock.h"
 #include "intel_tc.h"
 
-#define DP_PIN_ASSIGNMENT_NONE 0x0
-#define DP_PIN_ASSIGNMENT_C    0x3
-#define DP_PIN_ASSIGNMENT_D    0x4
-#define DP_PIN_ASSIGNMENT_E    0x5
-
 enum tc_port_mode {
        TC_PORT_DISCONNECTED,
        TC_PORT_TBT_ALT,
@@ -317,15 +312,15 @@ static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
                REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
 
        switch (pin_assignment) {
-       case DP_PIN_ASSIGNMENT_NONE:
+       case INTEL_TC_PIN_ASSIGNMENT_NONE:
                return 0;
        default:
                MISSING_CASE(pin_assignment);
                fallthrough;
-       case DP_PIN_ASSIGNMENT_D:
+       case INTEL_TC_PIN_ASSIGNMENT_D:
                return 2;
-       case DP_PIN_ASSIGNMENT_C:
-       case DP_PIN_ASSIGNMENT_E:
+       case INTEL_TC_PIN_ASSIGNMENT_C:
+       case INTEL_TC_PIN_ASSIGNMENT_E:
                return 4;
        }
 }
@@ -340,10 +335,10 @@ static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
        default:
                MISSING_CASE(pin_mask);
                fallthrough;
-       case DP_PIN_ASSIGNMENT_D:
+       case INTEL_TC_PIN_ASSIGNMENT_D:
                return 2;
-       case DP_PIN_ASSIGNMENT_C:
-       case DP_PIN_ASSIGNMENT_E:
+       case INTEL_TC_PIN_ASSIGNMENT_C:
+       case INTEL_TC_PIN_ASSIGNMENT_E:
                return 4;
        }
 }

diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index 26c4265368c1a5e95739274a33e42663823028bf..7ea7e81239710a2284c950fc094152e1fd921244 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -12,6 +12,75 @@ struct intel_crtc_state;
 struct intel_digital_port;
 struct intel_encoder;
 
+/*
+ * The following enum values must stay fixed, as they match the corresponding
+ * pin assignment fields in the PORT_TX_DFLEXPA1 and TCSS_DDI_STATUS registers.
+ */
+enum intel_tc_pin_assignment {            /* Lanes (a)   Signal/   Cable   Notes   */
+                                         /* DP    USB   Rate (b)  type            */
+       INTEL_TC_PIN_ASSIGNMENT_NONE = 0, /* 4     -     -         -       (c)     */
+       INTEL_TC_PIN_ASSIGNMENT_A,        /* 2/4   0     GEN2      TC->TC  (d,e)   */
+       INTEL_TC_PIN_ASSIGNMENT_B,        /* 1/2   1     GEN2      TC->TC  (d,f,g) */
+       INTEL_TC_PIN_ASSIGNMENT_C,        /* 4     0     DP2       TC->TC  (h)     */
+       INTEL_TC_PIN_ASSIGNMENT_D,        /* 2     1     DP2       TC->TC  (h,g)   */
+       INTEL_TC_PIN_ASSIGNMENT_E,        /* 4     0     DP2       TC->DP          */
+       INTEL_TC_PIN_ASSIGNMENT_F,        /* 2     1     GEN1/DP1  TC->DP  (d,g,i) */
+       /*
+        * (a) - DP unidirectional lanes, each lane using 1 differential signal
+        *       pair.
+        *     - USB SuperSpeed bidirectional lane, using 2 differential (TX and
+        *       RX) signal pairs.
+        *     - USB 2.0 (HighSpeed) unidirectional lane, using 1 differential
+        *       signal pair. Not indicated, this lane is always present on pin
+        *       assignments A-D and never present on pin assignments E/F.
+        * (b) - GEN1: USB 3.1 GEN1 bit rate (5 Gbps) and signaling. This
+        *             is used for transferring only a USB stream.
+        *     - GEN2: USB 3.1 GEN2 bit rate (10 Gbps) and signaling. This
+        *             allows transferring an HBR3 (8.1 Gbps) DP stream.
+        *     - DP1:  Display Port signaling defined by the DP v1.3 Standard,
+        *             with a maximum bit rate of HBR3.
+        *     - DP2:  Display Port signaling defined by the DP v2.1 Standard,
+        *             with a maximum bit rate defined by the DP Alt Mode
+        *             v2.1a Standard depending on the cable type as follows:
+        *             - Passive (Full-Featured) USB 3.2 GEN1
+        *               TC->TC cables (CC3G1-X)                        : UHBR10
+        *             - Passive (Full-Featured) USB 3.2/4 GEN2 and
+        *               Thunderbolt Alt Mode GEN2
+        *               TC->TC cables (CC3G2-X)                    all : UHBR10
+        *                                                    DP54 logo : UHBR13.5
+        *             - Passive (Full-Featured) USB4 GEN3+ and
+        *               Thunderbolt Alt Mode GEN3+
+        *               TC->TC cables (CC4G3-X)                    all : UHBR13.5
+        *                                                    DP80 logo : UHBR20
+        *             - Active Re-Timed or
+        *               Active Linear Re-driven (LRD)
+        *               USB3.2 GEN1/2 and USB4 GEN2+
+        *               TC->TC cables                              all : HBR3
+        *                                               with DP_BR CTS : UHBR10
+        *                                                    DP54 logo : UHBR13.5
+        *                                                    DP80 logo : UHBR20
+        *             - Passive/Active Re-Timed or
+        *               Active Linear Re-driven (LRD)
+        *               TC->DP cables         with DP_BR CTS/DP8K logo : HBR3
+        *                                               with DP_BR CTS : UHBR10
+        *                                                    DP54 logo : UHBR13.5
+        *                                                    DP80 logo : UHBR20
+        * (c) Used in TBT-alt/legacy modes and on LNL+ after the sink
+        *     disconnected in DP-alt mode.
+        * (d) Only defined by the DP Alt Standard v1.0a, deprecated by v1.0b,
+        *     only supported on ICL.
+        * (e) GEN2 passive 1 m cable: 4 DP lanes, GEN2 active cable: 2 DP lanes.
+        * (f) GEN2 passive 1 m cable: 2 DP lanes, GEN2 active cable: 1 DP lane.
+        * (g) These pin assignments are also referred to as (USB/DP)
+        *     multifunction or Multifunction Display Port (MFD) modes.
+        * (h) Also used where one end of the cable is a captive connector,
+        *     attached to a DP->HDMI/DVI/VGA converter.
+        * (i) The DP end of the cable is a captive connector attached to a
+        *     (DP/USB) multifunction dock as defined by the DockPort v1.0a
+        *     specification.
+        */
+};
+
 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port);
 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port);
 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port);