drm/mediatek: mtk_dpi: Support AFIFO 1T1P output and conversion

On some SoCs, like MT8195 and MT8188, the DPI's FIFO controller
(afifo) supports outputting either one or two pixels per round
regardless of the input being 1T1P or 1T2P.

Add a `output_1pixel` member to struct mtk_dpi_conf which, if
set, will enable outputting one pixel per clock.

In case the input is two pixel per clock (1T2P), the AFIFO HW
will automatically (and internally) convert it to 1T1P.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-9-angelogioacchino.delregno@collabora.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 91f3eb796219932b87def28c3c3f83d989ef994d..897ae591e61de6c276244dbc1c656c19cda03339 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -147,6 +147,8 @@ struct mtk_dpi_factor {
  * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
  * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, needed
  *                  for DPI registers access.
+ * @output_1pixel: Enable outputting one pixel per round; if the input is two pixel per
+ *                 round, the DPI hardware will internally transform it to 1T1P.
  */
 struct mtk_dpi_conf {
        const struct mtk_dpi_factor *dpi_factor;
@@ -168,6 +170,7 @@ struct mtk_dpi_conf {
        u32 pixels_per_iter;
        bool edge_cfg_in_mmsys;
        bool clocked_by_hdmi;
+       bool output_1pixel;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -653,7 +656,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
        if (dpi->conf->support_direct_pin) {
                mtk_dpi_config_yc_map(dpi, dpi->yc_map);
                mtk_dpi_config_2n_h_fre(dpi);
-               mtk_dpi_dual_edge(dpi);
+
+               /* DPI can connect to either an external bridge or the internal HDMI encoder */
+               if (dpi->conf->output_1pixel)
+                       mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
+               else
+                       mtk_dpi_dual_edge(dpi);
+
                mtk_dpi_config_disable_edge(dpi);
        }
        if (dpi->conf->input_2p_en_bit) {

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index a0b1d18bbbf7e5e994396e30656739dd378a8604..61b276bce70f8c3b985b02a12e551ab98ce79654 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -40,6 +40,10 @@
 #define FAKE_DE_LEVEN                  BIT(21)
 #define FAKE_DE_RODD                   BIT(22)
 #define FAKE_DE_REVEN                  BIT(23)
+
+/* DPI_CON: DPI instances */
+#define DPI_OUTPUT_1T1P_EN             BIT(24)
+/* DPI_CON: DPINTF instances */
 #define DPINTF_YUV422_EN               BIT(24)
 #define DPINTF_CSC_ENABLE              BIT(26)
 #define DPINTF_INPUT_2P_EN             BIT(29)