MBX Patch from Marius Gröger,

Tue, 14 Nov 2000 12:03:56

diff --git a/include/config_MBX.h b/include/config_MBX.h
index f5c7aa1576091e9cbdbf1691b79cca0c5ff2eb95..53bd3f06d930a8eb2d820f4efe18432f6c69ec7f 100644 (file)
--- a/include/config_MBX.h
+++ b/include/config_MBX.h
@@ -111,17 +111,10 @@
 #define        CFG_INIT_RAM_END        0x2f00  /* End of used area in DPRAM    */
 #define        CFG_INIT_DATA_SIZE      64  /* size in bytes reserved for initial data */
 #define CFG_INIT_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
-#define        CFG_INIT_SERIAL_SIZE    64  /* size in bytes reserved for serial rx/tx bd+buffers */
-#define CFG_INIT_SERIAL_OFFSET (CFG_INIT_DATA_OFFSET - CFG_INIT_SERIAL_SIZE)
 #define        CFG_INIT_VPD_SIZE       256 /* size in bytes reserved for vpd buffer */
-#define CFG_INIT_VPD_OFFSET    (CFG_INIT_SERIAL_OFFSET - CFG_INIT_VPD_SIZE)
+#define CFG_INIT_VPD_OFFSET    (CFG_INIT_DATA_OFFSET - CFG_INIT_VPD_SIZE)
 #define        CFG_INIT_SP_OFFSET      (CFG_INIT_VPD_OFFSET-8)
 
-/*-----------------------------------------------------------------------
- * Offset in DPMEM where we keep serial BDs and buffers
- */
-#define CFG_DPRAMSERIAL                (CFG_INIT_SERIAL_OFFSET - 0x2000)
-
 /*-----------------------------------------------------------------------
  * Offset in DPMEM where we keep the VPD data
  */
@@ -135,9 +128,9 @@
 #define        CFG_SDRAM_BASE          0x00000000
 #define CFG_FLASH_BASE         0xfe000000
 #ifdef DEBUG
-#define        CFG_MONITOR_LEN         (512 << 10)     /* Reserve 512 kB for Monitor   */
+#define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 #else
-#define        CFG_MONITOR_LEN         (512 << 10)     /* Reserve 512 kB for Monitor   */
+#define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 128 kB for Monitor   */
 #endif
 #undef  CFG_MONITOR_BASE       0x200000 /* to run ppcboot from RAM */
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
@@ -192,7 +185,7 @@
 #define CFG_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
                         SYPCR_SWE  | SYPCR_SWP)
 #else
-#define CFG_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CFG_SYPCR      (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -200,7 +193,8 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR     (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CFG_SIUMCR     (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | \
+                        SIUMCR_SEME)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control                                11-26
@@ -214,7 +208,7 @@
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR      (PISCR_PS | PISCR_PITF)
+#define CFG_PISCR      (PISCR_PS | PISCR_PITF | PISCR_PTE)
 
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register         15-30
@@ -230,7 +224,8 @@
  * Set clock output, timebase and RTC source and divider,
  * power management and some other internal clocks
  */
-#define CFG_SCCR       (SCCR_TBS | SCCR_COM11)
+#define SCCR_MASK      (SCCR_RTDIV | SCCR_RTSEL)
+#define CFG_SCCR       SCCR_TBS
 
 /*-----------------------------------------------------------------------
  * PCMCIA stuff

diff --git a/mbx8xx/mbx8xx.c b/mbx8xx/mbx8xx.c
index d788e36476ee9ca10f6071dba1b961fc10d958e9..68a5af76591118e552399ef20e5f87fcd08aa8a4 100644 (file)
--- a/mbx8xx/mbx8xx.c
+++ b/mbx8xx/mbx8xx.c
@@ -123,32 +123,17 @@ void mbx_init(void)
 {
     volatile immap_t *immr = (immap_t *)CFG_IMMR;
     volatile memctl8xx_t *memctl = &immr->im_memctl;
-    unsigned int speed, refclock, plprcr;
-
-#if 0 
-    /* SIUMCR - contains debug pin configuration (11-6) */
-    immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
-
-    /* timebase status and control register */
-    immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
-    immr->im_sit.sit_tbscr = 0xc3;
-    
-    /* pit status and control register */
-    immr->im_sitk.sitk_piscrk = KAPWR_KEY;
-    immr->im_sit.sit_piscr = CFG_PISCR;
-   
-    /* pll, low power, and reset control register */
-    immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
-
-    /* system clock and reset control register */
-    immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
-    immr->im_clkrst.car_sccr = CFG_SCCR;
-#endif
+    ulong speed, refclock, plprcr, sccr;
 
     /* real-time clock status and control register */
     immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
     immr->im_sit.sit_rtcsc = 0x00C3;
    
+    /* SIEL and SIMASK Registers (see MBX PRG 2-3) */
+    immr->im_siu_conf.sc_simask = 0x00000000;
+    immr->im_siu_conf.sc_siel = 0xAAAA0000;
+    immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
+
     /* 
      * Prepare access to i2c bus. The MBX offers 3 devices on the i2c
      * bus: 
@@ -159,6 +144,13 @@ void mbx_init(void)
      */
     vpd_init();
 
+    /* system clock and reset control register */
+    immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+    sccr = immr->im_clkrst.car_sccr;
+    sccr &= SCCR_MASK;
+    sccr |= CFG_SCCR;   
+    immr->im_clkrst.car_sccr = sccr;
+
     speed = board_get_cpufreq();
     refclock = get_reffreq();
 
@@ -190,8 +182,6 @@ void mbx_init(void)
     memctl->memc_or5 = CFG_PCIMEM_OR;
     memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
     memctl->memc_or6 = CFG_PCIBRIDGE_OR;
-
-    MBX_CSR1 = 0;
 }
 
 void board_serial_init(void)
@@ -201,8 +191,8 @@ void board_serial_init(void)
 
 void board_ether_init(void)
 {
-    MBX_CSR1 &= ~CSR1_EAEN | CSR1_ELEN;
-    MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
+    MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
+    MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS ;
 }
 
 static unsigned int board_get_cpufreq(void)
@@ -313,7 +303,7 @@ long int initdram (int board_type)
            upmconfig(UPMA, (uint *)sdram_table_40, 
                      sizeof(sdram_table_40) / sizeof(uint));
            memctl->memc_mptpr = 0x0200;
-           memctl->memc_mamr = dimm_sz ? 0x0682100 : 0x13801000;
+           memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
            memctl->memc_br0 = 0xfe000000 | br0_32            | 1;
            memctl->memc_or0 = 0xff800930;
            memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
@@ -323,7 +313,7 @@ long int initdram (int board_type)
            upmconfig(UPMA, (uint *)sdram_table_50, 
                      sizeof(sdram_table_50) / sizeof(uint));
            memctl->memc_mptpr = 0x0200;
-           memctl->memc_mamr = dimm_sz ? 0x0882100 : 0x1882100;
+           memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
            memctl->memc_br0 = 0xfe000000 |  br0_32           | 1;
            memctl->memc_or0 = 0xff800940;
            memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;

diff --git a/mpc8xx/serial.c b/mpc8xx/serial.c
index 81d75a9a1a58692ebc8319982b1a0dd191d5a948..9d9af0035b97f4f7fe90967eb8370d17ba194f34 100644 (file)
--- a/mpc8xx/serial.c
+++ b/mpc8xx/serial.c
@@ -128,7 +128,6 @@ serial_init (ulong cpu_clock, int baudrate)
 
 #if defined(CONFIG_MBX)
        board_serial_init();
-       dpaddr = CFG_DPRAMSERIAL;
 #endif /* CONFIG_MBX */
 
        /* Set the physical address of the host memory buffers in