drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_CRC_CTL register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2ac4438aa885be9d0fcf5c697beee99a4cd2c23f.1714990089.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 5a468ed6e26c71e862729724e3cba38aff4bf736..35c3dd1130ce6dcccd82fdbd4de907eb9313deb2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -608,8 +608,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
                goto out;
 
        pipe_crc->source = source;
-       intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
-       intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+       intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
+       intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
 
        if (!source) {
                if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
@@ -643,8 +643,8 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
        /* Don't need pipe_crc->lock here, IRQs are not generated. */
        pipe_crc->skipped = 0;
 
-       intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
-       intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+       intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val);
+       intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
 }
 
 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
@@ -658,7 +658,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
        pipe_crc->skipped = INT_MIN;
        spin_unlock_irq(&pipe_crc->lock);
 
-       intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
-       intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
+       intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0);
+       intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe));
        intel_synchronize_irq(dev_priv);
 }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae692f461982eb9a2820bfe752dea347d10a6692..4525afafc79f5d8730ef38989c8a30349556b3dd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1137,7 +1137,7 @@
 #define _PIPE_CRC_RES_4_B_IVB          0x61070
 #define _PIPE_CRC_RES_5_B_IVB          0x61074
 
-#define PIPE_CRC_CTL(pipe)             _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
+#define PIPE_CRC_CTL(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
 #define PIPE_CRC_RES_1_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB)
 #define PIPE_CRC_RES_2_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB)
 #define PIPE_CRC_RES_3_IVB(pipe)       _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB)