ice: dpll: fix output pin capabilities

The dpll output pins which are used to feed clock signal of PHY and MAC
circuits cannot be disconnected, those integrated circuits require clock
signal for operation.
By stopping assignment of DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE pin
capability, prevent the user from invoking the state set callback on
those pins, setting the state on those pins already returns error, as
firmware doesn't allow the change of their state.

Fixes: d7999f5ea64b ("ice: implement dpll interface to control cgu")
Fixes: 8a3a565ff210 ("ice: add admin commands to access cgu configuration")
Reviewed-by: Andrii Staikov <andrii.staikov@intel.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Tested-by: Sunitha Mekala <sunithax.d.mekala@intel.com> (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 831ba6683962ee50da433668fc13dd83b16e9e97..86b180cb32a027d38f8422bb8da1fe3a2d1c54ac 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -1823,6 +1823,7 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
        int num_pins, i, ret = -EINVAL;
        struct ice_hw *hw = &pf->hw;
        struct ice_dpll_pin *pins;
+       unsigned long caps;
        u8 freq_supp_num;
        bool input;
 
@@ -1842,6 +1843,7 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
        }
 
        for (i = 0; i < num_pins; i++) {
+               caps = 0;
                pins[i].idx = i;
                pins[i].prop.board_label = ice_cgu_get_pin_name(hw, i, input);
                pins[i].prop.type = ice_cgu_get_pin_type(hw, i, input);
@@ -1854,8 +1856,8 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
                                                      &dp->input_prio[i]);
                        if (ret)
                                return ret;
-                       pins[i].prop.capabilities |=
-                               DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
+                       caps |= (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |
+                                DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE);
                        pins[i].prop.phase_range.min =
                                pf->dplls.input_phase_adj_max;
                        pins[i].prop.phase_range.max =
@@ -1865,9 +1867,11 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
                                pf->dplls.output_phase_adj_max;
                        pins[i].prop.phase_range.max =
                                -pf->dplls.output_phase_adj_max;
+                       ret = ice_cgu_get_output_pin_state_caps(hw, i, &caps);
+                       if (ret)
+                               return ret;
                }
-               pins[i].prop.capabilities |=
-                       DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
+               pins[i].prop.capabilities = caps;
                ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
                if (ret)
                        return ret;

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 6d573908de7a0bf3690695e97ac191d8dec6f559..a00b55e14aac4e53806e22e9fcec377c5ffa9914 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -3961,3 +3961,57 @@ int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num)
 
        return ret;
 }
+
+/**
+ * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
+ * @hw: pointer to the hw struct
+ * @pin_id: id of a pin
+ * @caps: capabilities to modify
+ *
+ * Return:
+ * * 0 - success, state capabilities were modified
+ * * negative - failure, capabilities were not modified
+ */
+int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
+                                     unsigned long *caps)
+{
+       bool can_change = true;
+
+       switch (hw->device_id) {
+       case ICE_DEV_ID_E810C_SFP:
+               if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3)
+                       can_change = false;
+               break;
+       case ICE_DEV_ID_E810C_QSFP:
+               if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4)
+                       can_change = false;
+               break;
+       case ICE_DEV_ID_E823L_10G_BASE_T:
+       case ICE_DEV_ID_E823L_1GBE:
+       case ICE_DEV_ID_E823L_BACKPLANE:
+       case ICE_DEV_ID_E823L_QSFP:
+       case ICE_DEV_ID_E823L_SFP:
+       case ICE_DEV_ID_E823C_10G_BASE_T:
+       case ICE_DEV_ID_E823C_BACKPLANE:
+       case ICE_DEV_ID_E823C_QSFP:
+       case ICE_DEV_ID_E823C_SFP:
+       case ICE_DEV_ID_E823C_SGMII:
+               if (hw->cgu_part_number ==
+                   ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 &&
+                   pin_id == ZL_OUT2)
+                       can_change = false;
+               else if (hw->cgu_part_number ==
+                        ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 &&
+                        pin_id == SI_OUT1)
+                       can_change = false;
+               break;
+       default:
+               return -EINVAL;
+       }
+       if (can_change)
+               *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
+       else
+               *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
+
+       return 0;
+}

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
index 36aeeef99ec07e9b7bfdb63d175a1ad09188b71d..cf76701566c72479e7c8df5f2011c7ee1d146b6a 100644 (file)
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
@@ -282,6 +282,8 @@ int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
 
 void ice_ptp_init_phy_model(struct ice_hw *hw);
+int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
+                                     unsigned long *caps);
 
 #define PFTSYN_SEM_BYTES       4