static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
        .gen = 3,
        .features = RCAR_DU_FEATURE_CRTC_IRQ
-                 | RCAR_DU_FEATURE_VSP1_SOURCE,
+                 | RCAR_DU_FEATURE_VSP1_SOURCE
+                 | RCAR_DU_FEATURE_NO_BLENDING,
        .channels_mask = BIT(1) | BIT(0),
        .routes = {
                /* R8A779A0 has two MIPI DSI outputs. */
 
 #define RCAR_DU_FEATURE_VSP1_SOURCE    BIT(2)  /* Has inputs from VSP1 */
 #define RCAR_DU_FEATURE_INTERLACED     BIT(3)  /* HW supports interlaced */
 #define RCAR_DU_FEATURE_TVM_SYNC       BIT(4)  /* Has TV switch/sync modes */
+#define RCAR_DU_FEATURE_NO_BLENDING    BIT(5)  /* PnMR.SPIM does not have ALP nor EOR bits */
 
 #define RCAR_DU_QUIRK_ALIGN_128B       BIT(0)  /* Align pitches to 128 bytes */
 
 
                                            unsigned int index,
                                            const struct rcar_du_plane_state *state)
 {
-       rcar_du_plane_write(rgrp, index, PnMR,
-                           PnMR_SPIM_TP_OFF | state->format->pnmr);
+       struct rcar_du_device *rcdu = rgrp->dev;
+       u32 pnmr = state->format->pnmr | PnMR_SPIM_TP_OFF;
+
+       if (rcdu->info->features & RCAR_DU_FEATURE_NO_BLENDING) {
+               /* No blending. ALP and EOR are not supported. */
+               pnmr &= ~(PnMR_SPIM_ALP | PnMR_SPIM_EOR);
+       }
+
+       rcar_du_plane_write(rgrp, index, PnMR, pnmr);
 
        rcar_du_plane_write(rgrp, index, PnDDCR4,
                            state->format->edf | PnDDCR4_CODE);
         * register to 0 to avoid this.
         */
 
-       /* TODO: Check if alpha-blending should be disabled in PnMR. */
        rcar_du_plane_write(rgrp, index, PnALPHAR, 0);
 }