ret = -ETIMEDOUT;
        }
 
-       intel_dp->sink_crc.started = false;
  out:
        hsw_enable_ips(intel_crtc);
        return ret;
        u8 buf;
        int ret;
 
-       if (intel_dp->sink_crc.started) {
-               ret = intel_dp_sink_crc_stop(intel_dp);
-               if (ret)
-                       return ret;
-       }
-
        if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
                return -EIO;
 
        if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
                return -EIO;
 
+       if (buf & DP_TEST_SINK_START) {
+               ret = intel_dp_sink_crc_stop(intel_dp);
+               if (ret)
+                       return ret;
+       }
+
        hsw_disable_ips(intel_crtc);
 
        if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
        }
 
        intel_wait_for_vblank(dev, intel_crtc->pipe);
-       intel_dp->sink_crc.started = true;
        return 0;
 }
 
 
        M2_N2
 };
 
-struct sink_crc {
-       bool started;
-};
-
 struct intel_dp {
        uint32_t output_reg;
        uint32_t aux_ch_ctl_reg;
        /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
        uint8_t num_sink_rates;
        int sink_rates[DP_MAX_SUPPORTED_RATES];
-       struct sink_crc sink_crc;
        struct drm_dp_aux aux;
        uint8_t train_set[4];
        int panel_power_up_delay;