drm/amd/display: Drop legacy code

This commit removes code that are not used by display anymore.

Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index a15efadb9183080028fb696ca1d1eaa8fa2e85b5..75b9ec21f29785c59f414c6db9554a47bf296f7f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -178,10 +178,6 @@ struct stream_encoder_funcs {
        void (*stop_dp_info_packets)(
                struct stream_encoder *enc);
 
-       void (*reset_fifo)(
-               struct stream_encoder *enc
-       );
-
        void (*dp_blank)(
                struct dc_link *link,
                struct stream_encoder *enc);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index 7cb0ed61271688a58e071b4ddc855b6d9c89c5b3..361ad6b16b96837c50451bdc6b9c71e90873d3dd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -584,13 +584,6 @@ bool get_temp_dp_link_res(struct dc_link *link,
                struct link_resource *link_res,
                struct dc_link_settings *link_settings);
 
-#if defined(CONFIG_DRM_AMD_DC_FP)
-struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
-               const struct resource_context *res_ctx,
-               const struct resource_pool *pool,
-               const struct dc_link *link);
-#endif
-
 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
        struct dc_state *context);
 

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
index 58bdbd859bf9b0d4c95e992a355a434944deac78..d6f095b4555dca6ecb0f0aac5d9c48cecc473ece 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
@@ -462,16 +462,6 @@ void optc2_setup_manual_trigger(struct timing_generator *optc)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
-       /* Set the min/max selectors unconditionally so that
-        * DMCUB fw may change OTG timings when necessary
-        * TODO: Remove the w/a after fixing the issue in DMCUB firmware
-        */
-       REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-                                OTG_V_TOTAL_MIN_SEL, 1,
-                                OTG_V_TOTAL_MAX_SEL, 1,
-                                OTG_FORCE_LOCK_ON_EVENT, 0,
-                                OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
-
        REG_SET_8(OTG_TRIGA_CNTL, 0,
                        OTG_TRIGA_SOURCE_SELECT, 21,
                        OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 65d337731f5671102b4a4ff061b9688a29880dd2..8663cbc3d1cf5ea08ee923ad3b74383aed10ee78 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -581,32 +581,6 @@ static const struct resource_caps res_cap_rn = {
                .num_dsc = 3,
 };
 
-#ifdef DIAGS_BUILD
-static const struct resource_caps res_cap_rn_FPGA_4pipe = {
-               .num_timing_generator = 4,
-               .num_opp = 4,
-               .num_video_plane = 4,
-               .num_audio = 7,
-               .num_stream_encoder = 4,
-               .num_pll = 4,
-               .num_dwb = 1,
-               .num_ddc = 4,
-               .num_dsc = 0,
-};
-
-static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
-               .num_timing_generator = 2,
-               .num_opp = 2,
-               .num_video_plane = 2,
-               .num_audio = 7,
-               .num_stream_encoder = 2,
-               .num_pll = 4,
-               .num_dwb = 1,
-               .num_ddc = 4,
-               .num_dsc = 2,
-};
-#endif
-
 static const struct dc_plane_cap plane_cap = {
        .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
        .per_pixel_alpha = true,
@@ -1415,16 +1389,11 @@ static bool dcn21_resource_construct(
        struct dc_context *ctx = dc->ctx;
        struct irq_service_init_data init_data;
        uint32_t pipe_fuses = read_pipe_fuses(ctx);
-       uint32_t num_pipes;
+       uint32_t num_pipes = 0;
 
        ctx->dc_bios->regs = &bios_regs;
 
        pool->base.res_cap = &res_cap_rn;
-#ifdef DIAGS_BUILD
-       if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
-               //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
-               pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
-#endif
 
        pool->base.funcs = &dcn21_res_pool_funcs;