static int kv_init_fps_limits(struct amdgpu_device *adev);
 
 static void kv_dpm_powergate_uvd(void *handle, bool gate);
-static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
 
 
 static void kv_dpm_disable(struct amdgpu_device *adev)
 {
+       struct kv_power_info *pi = kv_get_pi(adev);
+
        amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
                       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
        amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
        /* powerup blocks */
        kv_dpm_powergate_acp(adev, false);
        kv_dpm_powergate_samu(adev, false);
-       kv_dpm_powergate_vce(adev, false);
+       if (pi->caps_vce_pg) /* power on the VCE block */
+               amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
        kv_dpm_powergate_uvd(adev, false);
 
        kv_enable_smc_cac(adev, false);
        int ret;
 
        if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
-               kv_dpm_powergate_vce(adev, false);
                if (pi->caps_stable_p_state)
                        pi->vce_boot_level = table->count - 1;
                else
                kv_enable_vce_dpm(adev, true);
        } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
                kv_enable_vce_dpm(adev, false);
-               kv_dpm_powergate_vce(adev, true);
        }
 
        return 0;
        }
 }
 
-static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
+static void kv_dpm_powergate_vce(void *handle, bool gate)
 {
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct kv_power_info *pi = kv_get_pi(adev);
-
-       if (pi->vce_power_gated == gate)
-               return;
+       int ret;
 
        pi->vce_power_gated = gate;
 
-       if (!pi->caps_vce_pg)
-               return;
-
-       if (gate)
-               amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
-       else
-               amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
+       if (gate) {
+               /* stop the VCE block */
+               ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+                                                            AMD_PG_STATE_GATE);
+               kv_enable_vce_dpm(adev, false);
+               if (pi->caps_vce_pg) /* power off the VCE block */
+                       amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
+       } else {
+               if (pi->caps_vce_pg) /* power on the VCE block */
+                       amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
+               kv_enable_vce_dpm(adev, true);
+               /* re-init the VCE block */
+               ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+                                                            AMD_PG_STATE_UNGATE);
+       }
 }
 
+
 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
 {
        struct kv_power_info *pi = kv_get_pi(adev);
        case AMD_IP_BLOCK_TYPE_UVD:
                kv_dpm_powergate_uvd(handle, gate);
                break;
+       case AMD_IP_BLOCK_TYPE_VCE:
+               kv_dpm_powergate_vce(handle, gate);
+               break;
        default:
                break;
        }