*/
        wmb();
 
-       writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
+       writel_relaxed(mmio_read_reg,
+                      ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 
+       mmiowb();
        for (i = 0; i < timeout; i++) {
                if (read_resp->req_id == mmio_read->seq_num)
                        break;
 
        /* write the aenq doorbell after all AENQ descriptors were read */
        mb();
-       writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
+       writel_relaxed((u32)aenq->head,
+                      dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
+       mmiowb();
 }
 
 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
 
        return io_sq->q_depth - 1 - cnt;
 }
 
-static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
+static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq,
+                                           bool relaxed)
 {
        u16 tail;
 
        pr_debug("write submission queue doorbell for queue: %d tail: %d\n",
                 io_sq->qid, tail);
 
-       writel(tail, io_sq->db_addr);
+       if (relaxed)
+               writel_relaxed(tail, io_sq->db_addr);
+       else
+               writel(tail, io_sq->db_addr);
 
        return 0;
 }
 
                 * issue a doorbell
                 */
                wmb();
-               ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
+               ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq, true);
+               mmiowb();
        }
 
        rx_ring->next_to_use = next_to_use;
 
        if (netif_xmit_stopped(txq) || !skb->xmit_more) {
                /* trigger the dma engine */
-               ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
+               ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq, false);
                u64_stats_update_begin(&tx_ring->syncp);
                tx_ring->tx_stats.doorbells++;
                u64_stats_update_end(&tx_ring->syncp);