cxl/test: Update test code for event records to CXL spec rev 3.1

Update test code for General Media, DRAM, Memory Module Event
Records to CXL spec rev 3.1.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Link: https://patch.msgid.link/20250111091756.1682-7-shiju.jose@huawei.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 347c1e7b37bdfa9c70c6b469ad987baa48ca35e4..8d731bd639882012df96c17c1e1de99301285c9d 100644 (file)
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -401,6 +401,10 @@ struct cxl_test_gen_media gen_media = {
                        .channel = 1,
                        .rank = 30,
                },
+               .component_id = { 0x3, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d },
+               .cme_threshold_ev_flags = 3,
+               .cme_count = { 33, 0, 0 },
+               .sub_type = 0x2,
        },
 };
 
@@ -429,6 +433,11 @@ struct cxl_test_dram dram = {
                .bank_group = 5,
                .bank = 2,
                .column = {0xDE, 0xAD},
+               .component_id = { 0x1, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d },
+               .sub_channel = 8,
+               .cme_threshold_ev_flags = 2,
+               .cvme_count = { 14, 0, 0 },
+               .sub_type = 0x5,
        },
 };
 
@@ -456,7 +465,10 @@ struct cxl_test_mem_module mem_module = {
                        .dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef },
                        .cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef },
                        .cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef },
-               }
+               },
+               /* .validity_flags = <set below> */
+               .component_id = { 0x2, 0x74, 0xc5, 0x8, 0x9a, 0x1a, 0xb, 0xfc, 0xd2, 0x7e, 0x2f, 0x31, 0x9b, 0x3c, 0x81, 0x4d },
+               .event_sub_type = 0x3,
        },
 };
 
@@ -478,13 +490,18 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds,
 
 static void cxl_mock_add_event_logs(struct mock_event_store *mes)
 {
-       put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK,
+       put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK |
+                          CXL_GMER_VALID_COMPONENT | CXL_GMER_VALID_COMPONENT_ID_FORMAT,
                           &gen_media.rec.media_hdr.validity_flags);
 
        put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP |
-                          CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN,
+                          CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN | CXL_DER_VALID_SUB_CHANNEL |
+                          CXL_DER_VALID_COMPONENT | CXL_DER_VALID_COMPONENT_ID_FORMAT,
                           &dram.rec.media_hdr.validity_flags);
 
+       put_unaligned_le16(CXL_MMER_VALID_COMPONENT | CXL_MMER_VALID_COMPONENT_ID_FORMAT,
+                          &mem_module.rec.validity_flags);
+
        mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed);
        mes_add_event(mes, CXL_EVENT_TYPE_INFO,
                      (struct cxl_event_record_raw *)&gen_media);