KVM: riscv: selftests: Add RISCV_SBI_EXT_REG

While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macros to set the new field appropriately. The
general CSR macro gets renamed to include "GENERAL", but the other
macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
index 5b62a3d2aa9b5ee193464e05ebc5df169a7ab4b0..e70ccda2011bf280c765e341f3986f9e4435577f 100644 (file)
--- a/tools/testing/selftests/kvm/include/riscv/processor.h
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -10,10 +10,10 @@
 #include "kvm_util.h"
 #include <linux/stringify.h>
 
-static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
-                                   uint64_t  size)
+static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
+                                   uint64_t idx, uint64_t size)
 {
-       return KVM_REG_RISCV | type | idx | size;
+       return KVM_REG_RISCV | type | subtype | idx | size;
 }
 
 #if __riscv_xlen == 64
@@ -22,24 +22,30 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
 #define KVM_REG_SIZE_ULONG     KVM_REG_SIZE_U32
 #endif
 
-#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
-                                            KVM_REG_RISCV_CONFIG_REG(name), \
-                                            KVM_REG_SIZE_ULONG)
+#define RISCV_CONFIG_REG(name)         __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0,           \
+                                                    KVM_REG_RISCV_CONFIG_REG(name),    \
+                                                    KVM_REG_SIZE_ULONG)
 
-#define RISCV_CORE_REG(name)   __kvm_reg_id(KVM_REG_RISCV_CORE, \
-                                            KVM_REG_RISCV_CORE_REG(name), \
-                                            KVM_REG_SIZE_ULONG)
+#define RISCV_CORE_REG(name)           __kvm_reg_id(KVM_REG_RISCV_CORE, 0,             \
+                                                    KVM_REG_RISCV_CORE_REG(name),      \
+                                                    KVM_REG_SIZE_ULONG)
 
-#define RISCV_CSR_REG(name)    __kvm_reg_id(KVM_REG_RISCV_CSR, \
-                                            KVM_REG_RISCV_CSR_REG(name), \
-                                            KVM_REG_SIZE_ULONG)
+#define RISCV_GENERAL_CSR_REG(name)    __kvm_reg_id(KVM_REG_RISCV_CSR,                 \
+                                                    KVM_REG_RISCV_CSR_GENERAL,         \
+                                                    KVM_REG_RISCV_CSR_REG(name),       \
+                                                    KVM_REG_SIZE_ULONG)
 
-#define RISCV_TIMER_REG(name)  __kvm_reg_id(KVM_REG_RISCV_TIMER, \
-                                            KVM_REG_RISCV_TIMER_REG(name), \
-                                            KVM_REG_SIZE_U64)
+#define RISCV_TIMER_REG(name)          __kvm_reg_id(KVM_REG_RISCV_TIMER, 0,            \
+                                                    KVM_REG_RISCV_TIMER_REG(name),     \
+                                                    KVM_REG_SIZE_U64)
 
-#define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \
-                                            idx, KVM_REG_SIZE_ULONG)
+#define RISCV_ISA_EXT_REG(idx)         __kvm_reg_id(KVM_REG_RISCV_ISA_EXT,             \
+                                                    KVM_REG_RISCV_ISA_SINGLE,          \
+                                                    idx, KVM_REG_SIZE_ULONG)
+
+#define RISCV_SBI_EXT_REG(idx)         __kvm_reg_id(KVM_REG_RISCV_SBI_EXT,             \
+                                                    KVM_REG_RISCV_SBI_SINGLE,          \
+                                                    idx, KVM_REG_SIZE_ULONG)
 
 /* L3 index Bit[47:39] */
 #define PGTBL_L3_INDEX_MASK                    0x0000FF8000000000ULL

diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index d146ca71e0c0948b74830ebc7f2c4f05e407a1aa..6c25f7843ef44af17ac96339990c0eea56a72482 100644 (file)
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -201,7 +201,7 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu)
        satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
        satp |= SATP_MODE_48;
 
-       vcpu_set_reg(vcpu, RISCV_CSR_REG(satp), satp);
+       vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp);
 }
 
 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
@@ -315,7 +315,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
        vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code);
 
        /* Setup default exception vector of guest */
-       vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap);
+       vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(stvec), (unsigned long)guest_unexp_trap);
 
        return vcpu;
 }