======================================================================
-Open Issues:
+Modifications for 1.1.4:
======================================================================
-* cpu/mpc8xx/soft_i2c.c - function write_addr(): accessing a
- non-existent device will cause an infinite loop
-
-* Enabling too many BOOTP Vendor Extensions easily overflows the 64
- byte limit imposed by the BOOTP header definition. While this is
- not a problem on our side, some DHCP servers will complain. Should
- we break up long BOOTP requests into several shorter ones?
+* Renamed board/ivms8 directory into board/ivm to fit better with new
+ configurations for IVMS8 and IVML24 systems
-* Boot with RAMDisk:
+* Added optional code to show boot progress by some (board-dependend)
+ function (for instance using some LED display, blink codes, etc).
+ Merged LED display code for HERMES board to use this new mechanism.
- No need to copy ramdisk image when it's already in RAM ??? Or do we
- have to move it out of the way if it's too low in memory?
+* Patch by Frank Gottschling, 11 Jan 2002:
+ add MHPC board
- No need to copy ramdisk image when it's in Flash/ROM ...
+* Patch by Patrick Coleman, 11 Jan 2002
+ Fix reset address for Motorola MPC8260 ADS board
-* Timer:
+* Patch by Patrick Coleman, 8 Jan 2002
+ Fixes to Motorola MPC8260 ADS board:
+ - fix flash_erase() timeout
+ - make sure that Block Lock Bit was cleared in flash_erase()
+ - check for block erase errors (SR.5) in flash_erase()
+ - reset Read Array and status register before starting erase
- don't use 'lr RX, const; mtdec RX" -> use:
- mfdec R3
- foo: add. R3,277000,R3 # 277,777 is base 10
- ble foo
- mtdec R3
- instead
-
-* loads:
-
- Printing error messages does not work because "cu" is eating all
- output.
-
-* saveenv:
-
- Can we create a ld script which automagically takes care about
- flash boot sector location, so that it makes code "flow" around the
- gap if there is one, instead of hard-coding the map - which will
- break if sizes change?
-
-* BUG:
-
- Fix Exception handling for "Software Emulation Exception" etc.
-
-======================================================================
-To do:
-======================================================================
-
-* Video extensions support (to pass framebuffer information to
- applications and linux kernel)
-
-* "last user address" is set even if bootp is used without parameters
- (and it uses default address).
-
-======================================================================
-Modifications for 1.1.4:
-======================================================================
+* Fix bug in interrupt handling in Walnut flash driver
+ Patch by Andrew May, 10 Jan 2002
* Fix Sandpoint8240 port: boots now from flash, without need for DINK
* bootm:
Make checksum verification of images optional (depending on
- "verify" environment variable?) to allow for fast boot is speed is
+ "verify" environment variable?) to allow for fast boot if speed is
more important than safety.
Done - Fri Aug 4 2000 - wd@denx.de
BUG: mkimage -d does not truncate an existing image
Done - Fri Aug 4 2000 - wd@denx.de
+
+======================================================================
+Open Issues:
+======================================================================
+
+* cpu/mpc8xx/soft_i2c.c - function write_addr(): accessing a
+ non-existent device will cause an infinite loop
+
+* Enabling too many BOOTP Vendor Extensions easily overflows the 64
+ byte limit imposed by the BOOTP header definition. While this is
+ not a problem on our side, some DHCP servers will complain. Should
+ we break up long BOOTP requests into several shorter ones?
+
+* Boot with RAMDisk:
+
+ No need to copy ramdisk image when it's already in RAM ??? Or do we
+ have to move it out of the way if it's too low in memory?
+
+ No need to copy ramdisk image when it's in Flash/ROM ...
+
+* Timer:
+
+ don't use 'lr RX, const; mtdec RX" -> use:
+ mfdec R3
+ foo: add. R3,277000,R3 # 277,777 is base 10
+ ble foo
+ mtdec R3
+ instead
+
+* loads:
+
+ Printing error messages does not work because "cu" is eating all
+ output.
+
+* saveenv:
+
+ Can we create a ld script which automagically takes care about
+ flash boot sector location, so that it makes code "flow" around the
+ gap if there is one, instead of hard-coding the map - which will
+ break if sizes change?
+
+* BUG:
+
+ Fix Exception handling for "Software Emulation Exception" etc.
+
+======================================================================
+To do:
+======================================================================
+
+* Video extensions support (to pass framebuffer information to
+ applications and linux kernel)
+
+* "last user address" is set even if bootp is used without parameters
+ (and it uses default address).
+
E: DGE@sixnetio.com
D: EEPROM Speedup, SXNI855T port
+N: Frank Gottschling
+E: fgottschling@eltec.de
+D: Support for ELTEC MHPC board
+W: www.eltec.de
+
N: Marius Groeger
E: mgroeger@sysgo.de
D: MBX Support, board specific function interface, EST SBC8260 support
cogent_mpc8xx ESTEEM192E ETX094 FADS823 \
FADS850SAR FADS860T FLAGADM FPS850L \
GENIETV GTH hermes ICU862 \
- IP860 IVML24 IVMS8 LANTEC \
- lwmon MBX MBX860T NX823 \
- pcu_e RPXlite SM850 SPD823TS \
- SXNI855T TQM823L TQM823L_LCD TQM850L \
- TQM855L TQM860L TQM860L_FEC \
+ IP860 IVML24 IVML24_128 IVML24_256 \
+ IVMS8 IVMS8_128 IVMS8_256 LANTEC \
+ lwmon MBX MBX860T MHPC \
+ NX823 pcu_e RPXlite SM850 \
+ SPD823TS SXNI855T TQM823L TQM823L_LCD \
+ TQM850L TQM855L TQM860L TQM860L_FEC \
"
#########################################################################
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+IVML24_256_config \
+IVML24_128_config \
IVML24_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = ivms8" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
- echo "#include <config_$(@:_config=).h>" >config.h
+ echo "BOARD = ivm" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk
+ @[ -z "$(findstring IVML24_config,$@)" ] || \
+ { echo "#define CONFIG_IVML24_16M" >include/config.h ; \
+ }
+ @[ -z "$(findstring IVML24_128_config,$@)" ] || \
+ { echo "#define CONFIG_IVML24_32M" >>include/config.h ; \
+ }
+ @[ -z "$(findstring IVML24_256_config,$@)" ] || \
+ { echo "#define CONFIG_IVML24_64M" >>include/config.h ; \
+ }
+ @echo "#include <config_IVML24.h>" >>include/config.h
+IVMS8_256_config \
+IVMS8_128_config \
IVMS8_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
echo "ARCH = ppc" > config.mk ; \
- echo "BOARD = ivms8" >>config.mk ; \
- echo "CPU = mpc8xx" >>config.mk ; \
- echo "#include <config_$(@:_config=).h>" >config.h
+ echo "BOARD = ivm" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk
+ @[ -z "$(findstring IVMS8_config,$@)" ] || \
+ { echo "#define CONFIG_IVMS8_16M" >include/config.h ; \
+ }
+ @[ -z "$(findstring IVMS8_128_config,$@)" ] || \
+ { echo "#define CONFIG_IVMS8_32M" >>include/config.h ; \
+ }
+ @[ -z "$(findstring IVMS8_256_config,$@)" ] || \
+ { echo "#define CONFIG_IVMS8_64M" >>include/config.h ; \
+ }
+ @echo "#include <config_IVMS8.h>" >>include/config.h
LANTEC_config : unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
-NX823_config : unconfig
+MHPC_config: unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd ./include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "VENDOR= eltec" >>config.mk ; \
+ echo "BOARD = mhpc" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
+NX823_config: unconfig
@echo "Configuring for $(@:_config=) Board..." ; \
cd ./include ; \
echo "ARCH = ppc" > config.mk ; \
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MHPC boards
+#
+
+TEXT_BASE = 0xfe000000
+//TEXT_BASE = 0x00200000
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+#include "linux/byteorder/swab.h"
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+ size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000);
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("INTEL "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F640J5 :
+ printf ("28F640J5 \n"); break;
+ default: printf ("Unknown Chip Type=0x%lXh
+\n",info->flash_id & FLASH_TYPEMASK); break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+ FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW)0xAA00AA00;
+ addr[0x2AAA] = (FPW)0x55005500;
+ addr[0x5555] = (FPW)0x90009000;
+
+ value = SWAP(addr[0]);
+
+ switch (value) {
+ case (FPW)INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW)0xFF00FF00; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ value = SWAP(addr[1]); /* device ID no swap !*/
+
+ switch (value) {
+ case (FPW)INTEL_ID_28F640J5 :
+ info->flash_id += FLASH_28F640J5 ;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW)0xFF00FF00; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, now, last;
+ int rc = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *)(info->start[sect]);
+ FPW status;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = (FPW)0x50005000; /* clear status register */
+ *addr = (FPW)0x20002000; /* erase setup */
+ *addr = (FPW)0xD000D000; /* erase confirm */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW)0xB000B000; /* suspend erase */
+ *addr = (FPW)0xFF00FF00; /* reset to read mode */
+ rc = 1;
+ break;
+ }
+
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ *addr = (FPW)0xFF00FF00; /* reset to read mode */
+ printf (" done\n");
+ }
+ }
+ return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<port_width && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_data(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i=0; i<port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if ((wp & 0xfff) == 0)
+ {
+ printf("%08lX",wp);
+ printf("\x1b[8D");
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *)dest;
+ ulong status;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = (FPW)0x40004000; /* write setup */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+
+ while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW)0xFF00FF00; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = (FPW)0xFF00FF00; /* restore read mode */
+
+ return (0);
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * Board specific routines for the miniHiPerCam
+ *
+ * - initialisation (eeprom)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <stdarg.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+
+#include <ppcboot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+#include "rev.h"
+
+/* imports from common/main.c */
+extern char console_buffer[CFG_CBSIZE];
+
+extern void eeprom_init (void);
+extern void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
+extern void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt);
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static const uint sdram_table[] =
+{
+ /* read single beat cycle */
+ 0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
+ 0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
+
+ /* read burst cycle */
+ 0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
+ 0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* write single beat cycle */
+ 0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* write burst cycle */
+ 0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
+ 0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* periodic timer expired */
+ 0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
+ 0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
+ 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+ /* exception */
+ 0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
+};
+
+/* ------------------------------------------------------------------------- */
+
+int board_pre_init (void)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile cpm8xx_t *cp = &(im->im_cpm);
+ volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
+
+ /* reset the port A s.a. cpm-routines */
+ ip->iop_padat = 0x0000;
+ ip->iop_papar = 0x0000;
+ ip->iop_padir = 0x0800;
+ ip->iop_paodr = 0x0000;
+
+ /* reset the port B for digital and LCD output */
+ cp->cp_pbdat = 0x0300;
+ cp->cp_pbpar = 0x5001;
+ cp->cp_pbdir = 0x5301;
+ cp->cp_pbodr = 0x0000;
+
+ /* reset the port C configured for SMC1 serial port and aqc. control */
+ ip->iop_pcdat = 0x0800;
+ ip->iop_pcpar = 0x0000;
+ ip->iop_pcdir = 0x0e30;
+ ip->iop_pcso = 0x0000;
+
+ /* Config port D for LCD output */
+ ip->iop_pdpar = 0x1fff;
+ ip->iop_pddir = 0x1fff;
+
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+ revinfo mhpcRevInfo;
+ char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+ "OMNIVISON OV7110 b&w",
+ NULL };
+#endif
+
+ printf ("ELTEC miniHiperCam\n");
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+ eeprom_init ();
+ eeprom_read (480, (char*)&mhpcRevInfo, 32);
+
+ /* is eeprom initialized ? */
+ if (strncmp((char *)&mhpcRevInfo.board[2], "MHPC", 4) == 0)
+ {
+ printf (" Revision: %d.%c\n", mhpcRevInfo.revision[0],
+ mhpcRevInfo.revision[1]);
+ printf (" Order #: %s\n", (char *)&mhpcRevInfo.board);
+ printf (" Sensor : %s\n",
+ (mhpcRevInfo.sensor < (sizeof(mhpcSensorTypes)-1)) ?
+ mhpcSensorTypes[(int)mhpcRevInfo.sensor] :
+ "Sensor type unknown");
+ printf (" Serial #: %s\n", (char *)&mhpcRevInfo.serial);
+ printf (" Etheradr: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+ mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+ mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+ }
+ else
+ {
+ printf("\nRevision eeprom not initialized !\n");
+ }
+#endif
+
+ return(1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void
+misc_init_r(bd_t *bd)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+ revinfo mhpcRevInfo;
+ char nid[32];
+ char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+ "OMNIVISON OV7110 b&w",
+ NULL };
+ char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+ 0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+ int i;
+
+ /*
+ * check revision data
+ */
+ eeprom_read (480, (char*)&mhpcRevInfo, 32);
+
+ if (strncmp((char *)&mhpcRevInfo.board[2], "MHPC", 4) != 0)
+ {
+ printf ("Enter revision number (0-255): %d ", mhpcRevInfo.revision[0]);
+ if (0 != readline (NULL))
+ {
+ mhpcRevInfo.revision[0] =
+ (unsigned char)simple_strtoul(console_buffer, NULL, 10);
+ }
+
+ printf ("Enter revision character (A-Z): %c ", mhpcRevInfo.revision[1]);
+ if (1 == readline (NULL))
+ {
+ mhpcRevInfo.revision[1] = (char)toupper(console_buffer[0]);
+ }
+
+ printf("Enter board name (V-XXXX-XXXX): %s ", (char *)&mhpcRevInfo.board);
+ if (11 == readline (NULL))
+ {
+ for (i=0; i<11; i++)
+ {
+ mhpcRevInfo.board[i] = (char)toupper(console_buffer[i]);
+ mhpcRevInfo.board[11] = '\0';
+ }
+ }
+
+ printf("Supported sensor types:\n");
+ i=0;
+ do
+ {
+ printf("\n \'%d\' : %s\n", i, mhpcSensorTypes[i]);
+ } while ( mhpcSensorTypes[++i] != NULL );
+
+ do
+ {
+ printf("\nEnter sensor number (0-255): %d ", (int)mhpcRevInfo.sensor );
+ if (0 != readline (NULL))
+ {
+ mhpcRevInfo.sensor = (unsigned char)simple_strtoul(console_buffer, NULL, 10);
+ }
+ } while ( mhpcRevInfo.sensor >= i );
+
+ printf("Enter serial number: %s ", (char *)&mhpcRevInfo.serial );
+ if (6 == readline (NULL))
+ {
+ for (i=0; i<6; i++)
+ {
+ mhpcRevInfo.serial[i] = console_buffer[i];
+ }
+ mhpcRevInfo.serial[6] = '\0';
+ }
+
+ printf("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ",
+ mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+ mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+ mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5] );
+ if (12 == readline (NULL))
+ {
+ for (i=0; i<12; i+=2)
+ {
+ mhpcRevInfo.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
+ hex[toupper(console_buffer[i+1])-'0']);
+ }
+ }
+
+ /*
+ * setup new revision data
+ */
+ eeprom_write (480, (char*)&mhpcRevInfo, 32);
+ }
+
+ /*
+ *set environment
+ */
+ sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+ mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+ mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+ mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+ setenv("ethaddr", nid);
+
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mbmr = MAMR_GPL_B4DIS;
+ memctl->memc_mptpr = MPTPR_PTP_DIV64;
+ memctl->memc_mar = 0x00008800;
+
+ /*
+ * Map controller SDRAM bank 0
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+ udelay(200);
+
+ /*
+ * Map controller SDRAM bank 1
+ */
+ memctl->memc_or2 = CFG_OR2;
+ memctl->memc_br2 = CFG_BR2;
+
+ /*
+ * Perform SDRAM initializsation sequence
+ */
+ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
+ udelay(1);
+ memctl->memc_mcr = 0x80002730; /* SDRAM bank 0 - execute twice */
+ udelay(1);
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay(10000);
+
+ /* leave place for framebuffers */
+ return (SDRAM_MAX_SIZE-SDRAM_RES_SIZE);
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * revision info foer MHPC EEPROM offset 480
+ */
+typedef struct {
+ char board[12]; /* 000 - Board Revision information */
+ char sensor; /* 012 - Sensor Type information */
+ char serial[8]; /* 013 - Board serial number */
+ char etheraddr[6]; /* 021 - Ethernet node addresse */
+ char revision[2]; /* 027 - Revision code */
+ char option[3]; /* 029 - resevered for options */
+} revinfo;
+
+
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
- if (!i) {
+ if (i == -1) {
printf ("### No HW ID - assuming CPCI405");
}
-
- puts(str);
+ else
+ puts(str);
if (ctermm2())
printf(" (CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
#include <ppcboot.h>
#include <config.h>
-#include "mpc8xx.h"
+#include <mpc8xx.h>
#include "fads.h"
/* ------------------------------------------------------------------------- */
}
#endif /* CFG_CMD_PCMCIA */
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CFG_PC_IDE_RESET
+
+void ide_set_reset(int on)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ /*
+ * Configure PC for IDE Reset Pin
+ */
+ if (on) { /* assert RESET */
+ immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+ } else { /* release RESET */
+ immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+ }
+
+ /* program port pin as GPIO output */
+ immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+}
+
+#endif /* CFG_PC_IDE_RESET */
+/* ------------------------------------------------------------------------- */
#include <ppcboot.h>
#include <commproc.h>
-#include "mpc8xx.h"
+#include <mpc8xx.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
/* ------------------------------------------------------------------------- */
/* both 10 and 100 Mbps allowed:
* select 10 Mbps and autonegotiation
*/
-puts (" [10+100]");
+ puts (" [10+100]");
immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
speed = 10;
} else if (ethspeed == 10) {
/* we are asked for 10 Mbps,
* so select 10 Mbps
*/
-puts (" [10]");
+ puts (" [10]");
immr->im_cpm.cp_pbdat = 0; /* ??? */
speed = 10;
} else {
/* anything else:
* select 100 Mbps
*/
-puts (" [100]");
+ puts (" [100]");
immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
/* SPD1:SPD0 = 1:1 - 100 Mbps */
speed = 100;
/* both 10 and 100 Mbps allowed:
* select 100 Mbps and autonegotiation
*/
-puts (" [10+100]");
+ puts (" [10+100]");
immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
immr->im_ioport.iop_pcdat |= PC_REP_SPD;
} else if (ethspeed == 10) {
/* we are asked for 10 Mbps,
* so select 10 Mbps
*/
-puts (" [10]");
+ puts (" [10]");
immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
} else {
/* anything else:
* select 100 Mbps
*/
-puts (" [100]");
+ puts (" [100]");
immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
/* SPD1:SPD0 = 1:1 - 100 Mbps */
immr->im_ioport.iop_pcdat |= PC_REP_SPD;
immr->im_ioport.iop_pcdat |= PC_REP_RES;
}
}
- hermes_set_led (0);
+ SHOW_BOOT_PROGRESS (0x00);
return ((revision << 16) | (speed & 0xFFFF));
}
/* ------------------------------------------------------------------------- */
-void hermes_set_led (int code)
-{
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
- code ^= 0x0F;
- code = (code & 0x0F) << 14;
- immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | code;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void hermes_show_led_err (int code)
+void show_boot_progress (int status)
{
- int i;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
- for (;;) {
- hermes_set_led (code);
- for (i=0;i<100000;i++);
- hermes_set_led (0);
- for (i=0;i<100000;i++);
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-void hermes_flash_led (void)
-{
- int i;
- int led=0;
-
- for (;;) {
- hermes_set_led (1 << led);
- for (i=0;i<100000;i++);
- led = (led + 1) & 3;
- }
+ status ^= 0x0F;
+ status = (status & 0x0F) << 14;
+ immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) |
+ status;
}
/* ------------------------------------------------------------------------- */
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IVM boards
+#
+
+TEXT_BASE = 0xFF000000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size_b0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0: "
+ "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+ flash_info[0].flash_id,
+ size_b0, size_b0<<20);
+ }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \
+ BR_MS_GPCM | BR_PS_16 | BR_V;
+
+ /* Re-do sizing to get full correct info */
+ size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_MT:
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + ((i-3) * 0x00020000);
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+ return;
+
+ case FLASH_MAN_SST:
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00002000);
+ }
+ return;
+
+ case FLASH_MAN_AMD:
+ case FLASH_MAN_FUJ:
+
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+ return;
+ default:
+ printf ("Don't know sector ofsets for flash type 0x%lx\n",
+ info->flash_id);
+ return;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("STM "); break;
+ case FLASH_MAN_MT: printf ("MT "); break;
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n");
+ break;
+ case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n");
+ break;
+ case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n");
+ break;
+ case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n");
+ break;
+ case FLASH_28F008S5: printf ("28F008S5 (1M = 64K x 16)\n");
+ break;
+ case FLASH_28F400_T: printf ("28F400B3 (4Mbit, top boot sector)\n");
+ break;
+ case FLASH_28F400_B: printf ("28F400B3 (4Mbit, bottom boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ if (info->size >= (1 << 20)) {
+ i = 20;
+ } else {
+ i = 10;
+ }
+ printf (" Size: %ld %cB in %d Sectors\n",
+ info->size >> i,
+ (i == 20) ? 'M' : 'k',
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ ushort value;
+ vu_short *saddr = (vu_short *)addr;
+
+ /* Read Manufacturer ID */
+ saddr[0] = 0x0090;
+ value = saddr[0];
+
+ switch (value) {
+ case (AMD_MANUFACT & 0xFFFF):
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FUJ_MANUFACT & 0xFFFF):
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (SST_MANUFACT & 0xFFFF):
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (STM_MANUFACT & 0xFFFF):
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (MT_MANUFACT & 0xFFFF):
+ info->flash_id = FLASH_MAN_MT;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ saddr[0] = 0x00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ value = saddr[1]; /* device ID */
+
+ switch (value) {
+ case (AMD_ID_LV400T & 0xFFFF):
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (AMD_ID_LV400B & 0xFFFF):
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (AMD_ID_LV800T & 0xFFFF):
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (AMD_ID_LV800B & 0xFFFF):
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (AMD_ID_LV160T & 0xFFFF):
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (AMD_ID_LV160B & 0xFFFF):
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#if 0 /* enable when device IDs are available */
+ case (AMD_ID_LV320T & 0xFFFF):
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case (AMD_ID_LV320B & 0xFFFF):
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+ case (SST_ID_xF200A & 0xFFFF):
+ info->flash_id += FLASH_SST200A;
+ info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */
+ info->size = 0x00080000;
+ break;
+ case (SST_ID_xF400A & 0xFFFF):
+ info->flash_id += FLASH_SST400A;
+ info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */
+ info->size = 0x00100000;
+ break;
+ case (SST_ID_xF800A & 0xFFFF):
+ info->flash_id += FLASH_SST800A;
+ info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case (STM_ID_x800AB & 0xFFFF):
+ info->flash_id += FLASH_STM800AB;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case (MT_ID_28F400_T & 0xFFFF):
+ info->flash_id += FLASH_28F400_T;
+ info->sector_count = 7;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+ case (MT_ID_28F400_B & 0xFFFF):
+ info->flash_id += FLASH_28F400_B;
+ info->sector_count = 7;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ saddr[0] = 0x00FF; /* restore read mode */
+ return (0); /* => no or unknown flash */
+
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ saddr[0] = 0x00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) {
+ printf ("Can erase only MT flash types - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_short *addr = (vu_short *)(info->start[sect]);
+ unsigned short status;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = 0x0050; /* clear status register */
+ *addr = 0x0020; /* erase setup */
+ *addr = 0x00D0; /* erase confirm */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ while (((status = *addr) & 0x0080) != 0x0080) {
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0x00FF; /* reset to read mode */
+ return 1;
+ }
+
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ *addr = 0x00FF; /* reset to read mode */
+ }
+ }
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define FLASH_WIDTH 2 /* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+
+ wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<FLASH_WIDTH && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_data(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += FLASH_WIDTH;
+ }
+
+ /*
+ * handle FLASH_WIDTH aligned part
+ */
+ while (cnt >= FLASH_WIDTH) {
+ data = 0;
+ for (i=0; i<FLASH_WIDTH; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += FLASH_WIDTH;
+ cnt -= FLASH_WIDTH;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<FLASH_WIDTH; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_short *addr = (vu_short *)dest;
+ ushort sdata = (ushort)data;
+ ushort status;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & sdata) != sdata) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = 0x0040; /* write setup */
+ *addr = sdata;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+
+ while (((status = *addr) & 0x0080) != 0x0080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *addr = 0x00FF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = 0x00FF; /* restore read mode */
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+#ifdef CONFIG_STATUS_LED
+# include <status_led.h>
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+/*
+ * 50 MHz SHARC access using UPM A
+ */
+const uint sharc_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
+ 0xFFFFEC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+/*
+ * 50 MHz SDRAM access using UPM B
+ */
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
+ _NOT_USED_,
+ /*
+ * SDRAM Initialization (offset 5 in UPM RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
+ 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
+ 0xE1BBBC04, 0x1FF77C45, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
+ 0xFFFFFC05, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7FFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+#ifdef CONFIG_IVMS8
+ printf ("IVMS8\n");
+#endif
+#ifdef CONFIG_IVML24
+ printf ("IVM-L8/24\n");
+#endif
+ return (1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int
+initdram (int board_type)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ long int size_b0;
+
+ /* enable SDRAM clock ("switch on" SDRAM) */
+ immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
+ immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE ; /* output */
+ immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE ; /* assert SDRAM CLKE */
+ udelay(1);
+
+ /*
+ * Map controller bank 1 for ELIC SACCO
+ */
+ memctl->memc_or1 = CFG_OR1;
+ memctl->memc_br1 = CFG_BR1;
+
+ /*
+ * Map controller bank 2 for ELIC EPIC
+ */
+ memctl->memc_or2 = CFG_OR2;
+ memctl->memc_br2 = CFG_BR2;
+
+ /*
+ * Configure UPMA for SHARC
+ */
+ upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
+
+#if defined(CONFIG_IVML24)
+ /*
+ * Map controller bank 4 for HDLC Address space
+ */
+ memctl->memc_or4 = CFG_OR4;
+ memctl->memc_br4 = CFG_BR4;
+#endif
+
+ /*
+ * Map controller bank 5 for SHARC
+ */
+ memctl->memc_or5 = CFG_OR5;
+ memctl->memc_br5 = CFG_BR5;
+
+ memctl->memc_mamr = 0x00001000;
+
+ /*
+ * Configure UPMB for SDRAM
+ */
+ upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller bank 3 to the SDRAM bank at preliminary address.
+ */
+ memctl->memc_or3 = CFG_OR3_PRELIM;
+ memctl->memc_br3 = CFG_BR3_PRELIM;
+
+ memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+
+ udelay(200);
+ memctl->memc_mcr = 0x80806105; /* precharge */
+ udelay(1);
+ memctl->memc_mcr = 0x80806106; /* load mode register */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+ udelay(1);
+ memctl->memc_mcr = 0x80806130; /* autorefresh */
+
+ memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ */
+ size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
+
+ return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immr->im_memctl;
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
+
+ memctl->memc_mbmr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+ *addr = save[--i];
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ return (maxsize);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+ immap_t *immr = (immap_t *)CFG_IMMR;
+
+ /* De-assert Ethernet Powerdown */
+ immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
+ immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN ; /* output */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+ udelay(1000);
+
+ /*
+ * RESET is implemented by a positive pulse of at least 1 us
+ * at the reset pin.
+ *
+ * Configure RESET pins for NS DP83843 PHY, and RESET chip.
+ *
+ * Note: The RESET pin is high active, but there is an
+ * inverter on the SPD823TS board...
+ */
+ immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
+ immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
+ /* assert RESET signal of PHY */
+ immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
+ udelay (10);
+ /* de-assert RESET signal of PHY */
+ immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
+ udelay (10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void show_boot_progress (int status)
+{
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_YELLOW)
+ status_led_set (STATUS_LED_YELLOW,
+ (status < 0) ? STATUS_LED_OFF : STATUS_LED_ON);
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+void ide_set_reset(int on)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ /*
+ * Configure PC for IDE Reset Pin
+ */
+ if (on) { /* assert RESET */
+ immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+ } else { /* release RESET */
+ immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+ }
+
+ /* program port pin as GPIO output */
+ immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc8xx/start.o (.text)
+ common/environment.o(.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/vsprintf.o (.text)
+ ppc/crc32.o (.text)
+ ppc/extable.o (.text)
+
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
/*-----------------------------------------------------------------------
*/
printf ("\n");
}
- start = get_timer (0);
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long *)(info->start[sect]);
+ last = start = get_timer (0);
+
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
+ /* Reset Array */
+ *addr = 0xffffffff;
+ /* Clear Status Register */
+ *addr = 0x50505050;
/* Single Block Erase Command */
*addr = 0x20202020;
/* Confirm */
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
while ((*addr & 0x80808080) != 0x80808080) {
+ if(*addr & 0x20202020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ return 1;
+ }
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
*addr = 0xFFFFFFFF; /* reset bank */
}
}
if (csr & 0x40404040) {
-printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
flag = 1;
}
}
/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
*/
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ /* Clear Status Register */
+ *addr = 0x50505050;
+
+ *addr = 0x60606060;
+ *addr = 0xd0d0d0d0;
+
+ start = get_timer (0);
+ while(*addr != 0x80808080){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ return 1;
+ }
+ }
+ return 0;
+}
goto Done;
}
- pci_config_inl(bus, devno, func, PCI_CFG_BASE_ADDRESS_0, &iobase);
+ pci_config_inl (bus, devno, func,
+ PCI_CFG_BASE_ADDRESS_0, (uint32 *)&iobase);
iobase &= PCI_MEMBASE_MASK;
- printf("eth: Intel i82559 PCI EtherExpressPro @0x%x"
+ printf("eth: Intel i82559 PCI EtherExpressPro @0x%lX"
"(bus=%d, device=%d, func=%d)\n",
iobase, bus, devno, func);
/* Check if I/O accesses and Bus Mastering are enabled.
*/
- pci_config_inl(bus, devno, func, PCI_CFG_COMMAND, &status);
+ pci_config_inl (bus, devno, func,
+ PCI_CFG_COMMAND, &status);
+
if (!(status & PCI_CMD_MEM_ENABLE))
{
printf("Error: Can not enable MEM access.\n");
*/
int pci_dev_init(int busNo)
{
- int deviceNo, a;
- uint32 cmd, bar;
+ int deviceNo;
int devices;
uint16 vendorId;
uint16 deviceId;
int checkboard (void)
{
- printf("Sandpoint ");
- /*TODO: Check processor type*/
- printf("8240 Unity ##Test not implemented yet##\n");
- return 0;
+ printf ("Sandpoint ");
+ /*TODO: Check processor type */
+ printf ("8240 Unity ##Test not implemented yet##\n");
+ return 0;
}
int checkflash (void)
{
- /* TODO: XXX XXX XXX */
- printf ("## Test not implemented yet ##\n");
+ /* TODO: XXX XXX XXX */
+ printf ("## Test not implemented yet ##\n");
- return (0);
+ return (0);
}
-static long
-dram_size(void)
+static long dram_size (void)
{
- static const unsigned long
- addressmask = 0x4ff00000,
- addressinc = 0x00100000;
- long result = 0;
+ static const unsigned long
+ addressmask = 0x4ff00000, addressinc = 0x00100000;
+ long result = 0;
#if (CFG_BANK_ENABLE & 0x80)
- result += (CFG_BANK7_END & addressmask) + addressinc - (CFG_BANK7_START & addressmask);
+ result += (CFG_BANK7_END & addressmask) + addressinc -
+ (CFG_BANK7_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x40)
- result += (CFG_BANK6_END & addressmask) + addressinc - (CFG_BANK6_START & addressmask);
+ result += (CFG_BANK6_END & addressmask) + addressinc -
+ (CFG_BANK6_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x20)
- result += (CFG_BANK5_END & addressmask) + addressinc - (CFG_BANK5_START & addressmask);
+ result += (CFG_BANK5_END & addressmask) + addressinc -
+ (CFG_BANK5_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x10)
- result += (CFG_BANK4_END & addressmask) + addressinc - (CFG_BANK4_START & addressmask);
+ result += (CFG_BANK4_END & addressmask) + addressinc -
+ (CFG_BANK4_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x08)
- result += (CFG_BANK3_END & addressmask) + addressinc - (CFG_BANK3_START & addressmask);
+ result += (CFG_BANK3_END & addressmask) + addressinc -
+ (CFG_BANK3_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x04)
- result += (CFG_BANK2_END & addressmask) + addressinc - (CFG_BANK2_START & addressmask);
+ result += (CFG_BANK2_END & addressmask) + addressinc -
+ (CFG_BANK2_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x02)
- result += (CFG_BANK1_END & addressmask) + addressinc - (CFG_BANK1_START & addressmask);
+ result += (CFG_BANK1_END & addressmask) + addressinc -
+ (CFG_BANK1_START & addressmask);
#endif
#if (CFG_BANK_ENABLE & 0x01)
- result += (CFG_BANK0_END & addressmask) + addressinc - (CFG_BANK0_START & addressmask);
+ result += (CFG_BANK0_END & addressmask) + addressinc -
+ (CFG_BANK0_START & addressmask);
#endif
- return result;
+ return result;
}
-long int initdram(int board_type)
+long int initdram (int board_type)
{
- return dram_size();
+ return dram_size ();
}
/*
* Initialize PCI Devices, report devices found.
*/
-void pci_init (bd_t *dummy)
+void pci_init (bd_t * dummy)
{
- pci_dev_init(0);
+ extern int pci_dev_init (int busNo);
+
+ pci_dev_init (0);
}
immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
udelay (10);
}
+
+/* ------------------------------------------------------------------------- */
+
+void ide_set_reset(int on)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ /*
+ * Configure PC for IDE Reset Pin
+ */
+ if (on) { /* assert RESET */
+ immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+ } else { /* release RESET */
+ immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+ }
+
+ /* program port pin as GPIO output */
+ immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+}
+
+/* ------------------------------------------------------------------------- */
* 1 - write timeout
* 2 - Flash not erased
*/
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word (flash_info_t * info, ulong dest, ulong data)
{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
- int flag;
- int i;
+ int i;
/* Check if Flash is (sufficiently) erased */
- if ((*((volatile FLASH_WORD_SIZE *)dest) &
- (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
- {
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
return (0);
}
#ifdef CFG_HUSH_PARSER
#include <hush.h>
#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
int gunzip (void *, int, unsigned char *, int *);
static void *zalloc(void *, unsigned, unsigned);
addr = simple_strtoul(argv[1], NULL, 16);
}
-#ifdef CONFIG_HERMES
- hermes_set_led (1);
-#endif
+ SHOW_BOOT_PROGRESS (1);
printf ("## Booting image at %08lx ...\n", addr);
/* Copy header so we can blank CRC field for re-calculation */
if (hdr->ih_magic != IH_MAGIC) {
printf ("Bad Magic Number\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
-#ifdef CONFIG_HERMES
- hermes_set_led (2);
-#endif
+ SHOW_BOOT_PROGRESS (2);
data = (ulong)&header;
len = sizeof(image_header_t);
if (crc32 (0, (char *)data, len) != checksum) {
printf ("Bad Header Checksum\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
-#ifdef CONFIG_HERMES
- hermes_set_led (3);
-#endif
+ SHOW_BOOT_PROGRESS (3);
/* for multi-file images we need the data part, too */
print_image_hdr ((image_header_t *)addr);
printf (" Verifying Checksum ... ");
if (crc32 (0, (char *)data, len) != hdr->ih_dcrc) {
printf ("Bad Data CRC\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
printf ("OK\n");
}
-#ifdef CONFIG_HERMES
- hermes_set_led (4);
-#endif
+ SHOW_BOOT_PROGRESS (4);
len_ptr = (ulong *)data;
if (hdr->ih_arch != IH_CPU_PPC) {
printf ("Unsupported Architecture\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
-#ifdef CONFIG_HERMES
- hermes_set_led (5);
-#endif
+ SHOW_BOOT_PROGRESS (5);
switch (hdr->ih_type) {
case IH_TYPE_STANDALONE: name = "Standalone Application";
data += 4;
break;
default: printf ("Wrong Image Type for %s command\n", cmdtp->name);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
-#ifdef CONFIG_HERMES
- hermes_set_led (6);
-#endif
+ SHOW_BOOT_PROGRESS (6);
/*
* We have reached the point of no return: we are going to
if (iflag)
enable_interrupts();
printf ("Unimplemented compression type %d\n", hdr->ih_comp);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
printf ("OK\n");
-#ifdef CONFIG_HERMES
- hermes_set_led (7);
-#endif
+ SHOW_BOOT_PROGRESS (7);
switch (hdr->ih_type) {
case IH_TYPE_STANDALONE:
if (iflag)
enable_interrupts();
printf ("Can't boot image type %d\n", hdr->ih_type);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
-#ifdef CONFIG_HERMES
- hermes_set_led (8);
-#endif
+ SHOW_BOOT_PROGRESS (8);
- switch (hdr->ih_os)
- {
+ switch (hdr->ih_os) {
default: /* handled by (original) Linux case */
case IH_OS_LINUX:
do_bootm_linux (cmdtp, bd, flag, argc, argv,
#endif /* CFG_CMD_ELF */
}
+ SHOW_BOOT_PROGRESS (-1);
#ifdef DEBUG
printf ("\n## Control returned to monitor - resetting...\n");
do_reset (cmdtp, bd, flag, argc, argv);
* Check if there is an initrd image
*/
if (argc >= 3) {
-#ifdef CONFIG_HERMES
- hermes_set_led (9);
-#endif
+ SHOW_BOOT_PROGRESS (9);
+
addr = simple_strtoul(argv[2], NULL, 16);
printf ("## Loading RAMDisk Image at %08lx ...\n", addr);
if (hdr->ih_magic != IH_MAGIC) {
printf ("Bad Magic Number\n");
+ SHOW_BOOT_PROGRESS (-1);
do_reset (cmdtp, bd, flag, argc, argv);
}
if (crc32 (0, (char *)data, len) != checksum) {
printf ("Bad Header Checksum\n");
+ SHOW_BOOT_PROGRESS (-1);
do_reset (cmdtp, bd, flag, argc, argv);
}
-#ifdef CONFIG_HERMES
- hermes_set_led (10);
-#endif
+ SHOW_BOOT_PROGRESS (10);
+
print_image_hdr (hdr);
data = addr + sizeof(image_header_t);
if (csum != hdr->ih_dcrc) {
printf ("Bad Data CRC\n");
+ SHOW_BOOT_PROGRESS (-1);
do_reset (cmdtp, bd, flag, argc, argv);
}
printf ("OK\n");
}
-#ifdef CONFIG_HERMES
- hermes_set_led (11);
-#endif
+
+ SHOW_BOOT_PROGRESS (11);
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_PPC) ||
(hdr->ih_type != IH_TYPE_RAMDISK) ) {
printf ("No Linux PPC Ramdisk Image\n");
+ SHOW_BOOT_PROGRESS (-1);
do_reset (cmdtp, bd, flag, argc, argv);
}
u_long tail = len_ptr[0] % 4;
int i;
-#ifdef CONFIG_HERMES
- hermes_set_led (13);
-#endif
+ SHOW_BOOT_PROGRESS (13);
+
/* skip kernel length and terminator */
data = (ulong)(&len_ptr[2]);
/* skip any additional image length fields */
/*
* no initrd image
*/
-#ifdef CONFIG_HERMES
- hermes_set_led (14);
-#endif
+ SHOW_BOOT_PROGRESS (14);
+
data = 0;
}
if (nsp >= sp)
initrd_start = nsp;
}
-#ifdef CONFIG_HERMES
- hermes_set_led (12);
-#endif
+
+ SHOW_BOOT_PROGRESS (12);
#ifdef DEBUG
printf ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
data, data + len - 1, len, len);
printf ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)kernel);
#endif
-#ifdef CONFIG_HERMES
- hermes_set_led (15);
-#endif
+ SHOW_BOOT_PROGRESS (15);
/*
* Linux Kernel Parameters:
printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n",
(ulong)loader);
-#ifdef CONFIG_HERMES
- hermes_set_led (15);
-#endif
+ SHOW_BOOT_PROGRESS (15);
/*
* NetBSD Stage-2 Loader Parameters:
#include <image.h>
#ifdef CONFIG_IDE_PCMCIA
# include <pcmcia.h>
-# ifdef CONFIG_8xx
-# include <mpc8xx.h>
-# endif
+#endif
+#ifdef CONFIG_8xx
+# include <mpc8xx.h>
#endif
#include <ide.h>
#include <ata.h>
#include <cmd_ide.h>
#include <cmd_disk.h>
-#include <cmd_pcmcia.h>
#ifdef CONFIG_STATUS_LED
# include <status_led.h>
#endif
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
#undef IDE_DEBUG
break;
default:
printf ("Usage:\n%s\n", cmdtp->usage);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
if (!boot_device) {
puts ("\n** No boot device **\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) {
printf ("\n** Device %d not available\n", dev);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
if (*ep) {
if (*ep != ':') {
puts ("\n** Invalid boot device, use `dev[:part]' **\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
part = simple_strtoul(++ep, NULL, 16);
}
if (get_partition_info (&ide_dev_desc[dev], part, &info)) {
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) {
printf ("\n** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info.type);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) {
printf ("** Read error on %d:%d\n", dev, part);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
cnt -= 1;
} else {
printf("\n** Bad Magic Number **\n");
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt,
(ulong *)(addr+info.blksz)) != cnt) {
printf ("** Read error on %d:%d\n", dev, part);
+ SHOW_BOOT_PROGRESS (-1);
return 1;
}
/* Select device
*/
- WATCHDOG_RESET();
udelay (100000); /* 100 ms */
outb (dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
- WATCHDOG_RESET();
udelay (100000); /* 100 ms */
i = 0;
do {
- WATCHDOG_RESET();
udelay (10000); /* 10 ms */
c = inb (dev, ATA_STATUS);
if (c & ATA_STAT_BUSY) {
printf ("IDE read: device %d not ready\n", device);
- goto RD_OUT;
+ break;
}
outb (device, ATA_SECT_CNT, 1);
if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
device, blknr, c);
- goto RD_OUT;
+ break;
}
input_data (device, buffer, ATA_SECTORWORDS);
++blknr;
buffer += ATA_SECTORWORDS;
}
-RD_OUT:
+
ide_led (DEVICE_LED(device), 0); /* LED off */
return (n);
}
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_IDE_RESET
-#ifdef CONFIG_IDE_RESET_ROUTINE
extern void ide_set_reset(int idereset);
-#endif
static void ide_reset (void)
{
- int i;
-#if defined(CFG_PC_IDE_RESET)
+#if defined(CFG_PB_12V_ENABLE) || defined(CFG_PB_IDE_MOTOR)
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
+ int i;
+
curr_device = -1;
for (i=0; i<CFG_IDE_MAXBUS; ++i)
ide_bus_ok[i] = 0;
for (i=0; i<CFG_IDE_MAXDEVICE; ++i)
ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
-#if defined(CFG_PC_IDE_RESET)
- /* Configure PC for IDE Reset Pin
- */
- immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); /* Set reset bit */
- immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; /* Make output */
-
- /* assert IDE RESET signal */
- immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
- udelay (20000);
- /* de-assert RESET signal of IDE */
- immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
-#else
-#ifdef CONFIG_IDE_RESET_ROUTINE
- ide_set_reset(1); /* assert reset */
- udelay (20000);
- /* de-assert RESET signal of IDE */
- ide_set_reset(0);
-#else
-#error IDE reset pin not configured
-#endif /* CONFIG_IDE_RESET_ROUTINE */
-#endif /* CFG_PC_IDE_RESET */
+ ide_set_reset (1); /* assert reset */
WATCHDOG_RESET();
#ifdef CFG_PB_12V_ENABLE
- /* We must wait at least 500 ms for the voltage to stabilize;
- */
- for (i=0; i<50; ++i) {
- udelay (10000);
- }
- WATCHDOG_RESET();
- immr->im_cpm.cp_pbdat |= CFG_PB_12V_ENABLE; /* 12V Enable output ON */
+ immr->im_cpm.cp_pbdat &= ~(CFG_PB_12V_ENABLE); /* 12V Enable output OFF */
immr->im_cpm.cp_pbpar &= ~(CFG_PB_12V_ENABLE);
immr->im_cpm.cp_pbodr &= ~(CFG_PB_12V_ENABLE);
immr->im_cpm.cp_pbdir |= CFG_PB_12V_ENABLE;
+
+ /* wait 500 ms for the voltage to stabilize
+ */
+ for (i=0; i<500; ++i) {
+ udelay (1000);
+ }
+
+ immr->im_cpm.cp_pbdat |= CFG_PB_12V_ENABLE; /* 12V Enable output ON */
#endif /* CFG_PB_12V_ENABLE */
#ifdef CFG_PB_IDE_MOTOR
- immr->im_cpm.cp_pbpar &= ~(CFG_PB_IDE_MOTOR); /* IDE Motor in pin */
+ /* configure IDE Motor voltage monitor pin as input */
+ immr->im_cpm.cp_pbpar &= ~(CFG_PB_IDE_MOTOR);
immr->im_cpm.cp_pbodr &= ~(CFG_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbdir &= ~(CFG_PB_IDE_MOTOR); /* input */
- if ((immr->im_cpm.cp_pbdat & CFG_PB_IDE_MOTOR) == 0) {
+ immr->im_cpm.cp_pbdir &= ~(CFG_PB_IDE_MOTOR);
+
+ /* wait up to 1 s for the motor voltage to stabilize
+ */
+ for (i=0; i<1000; ++i) {
+ if ((immr->im_cpm.cp_pbdat & CFG_PB_IDE_MOTOR) != 0) {
+ break;
+ }
+ udelay (1000);
+ }
+
+ if (i == 1000) { /* Timeout */
printf ("\nWarning: 5V for IDE Motor missing\n");
# ifdef CONFIG_STATUS_LED
# ifdef STATUS_LED_YELLOW
WATCHDOG_RESET();
+ /* de-assert RESET signal */
+ ide_set_reset(0);
+
/* wait 250 ms */
- for (i=0; i<25; ++i) {
- udelay (10000);
+ for (i=0; i<250; ++i) {
+ udelay (1000);
}
-
- WATCHDOG_RESET();
}
#endif /* CONFIG_IDE_RESET */
#include <net.h>
#endif
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
/*
* Table with supported baudrates (defined in config_xyz.h)
*/
puts ("Using default environment\n\n");
#else
puts ("*** Warning - bad CRC, using default environment\n\n");
+ SHOW_BOOT_PROGRESS (-1);
#endif
/*
* TODO: We should check here that the
defined(CONFIG_IVML24) || \
defined(CONFIG_IVMS8) || \
defined(CONFIG_LWMON) || \
+ defined(CONFIG_MHPC) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXLITE) || \
defined(CONFIG_SPD823TS) || \
#include <i2c.h>
/* define to enable debug messages */
-#define DEBUG_I2C
+#undef DEBUG_I2C
/* us to wait before checking the i2c */
#define DELAY_US 100000
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002f00)
-#endif /* CONFIG_NX823 */
+#endif /* CONFIG_NX823 */
/*** MBX ************************************************************/
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif /* CONFIG_MBX */
+/*** MHPC ********************************************************/
+
+#if defined(CONFIG_MHPC)
+/* This ENET stuff is for the MHPC with ethernet on SCC2.
+ * Note TENA is on Port B.
+ */
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
+#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
+#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
+#endif /* CONFIG_MHPC */
+
/*** RPXCLASSIC *****************************************************/
#ifdef CONFIG_RPXCLASSIC
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#ifdef DEBUG
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
-#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
+
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#ifdef DEBUG
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
-#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Configuation settings for the miniHiPerCam.
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
+#define CONFIG_MHPC 1 /* on a miniHiPerCam */
+#define CONFIG_BOARD_PRE_INIT 1 /* do special hardware init. */
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
+#undef CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+ "bootm"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+
+#undef CONFIG_UCODE_PATCH
+#define CONFIG_I2C 1 /* To enable I2C support */
+
+#define CONFIG_BR0_WORKAROUND 1
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_DATE | \
+ CFG_CMD_I2C | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_REGINFO )
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x300000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_I2C_SPEED 50000
+#define CFG_I2C_SLAVE 0xFE
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM 24C04 */
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+
+#if 0
+#define CFG_I2C_UCODE_PATCH 1 /* activate I2C microcode */
+#define CFG_I2C_DPMEM_OFFSET 0x1fc0 /* Where to relocate I2C(0x1fc0=DSP2) */
+#undef CFG_RCCR
+#endif
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Physical memory map
+ */
+#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xfe000000
+
+#define CFG_MONITOR_LEN 0x20000 /* Reserve 128 kB for Monitor */
+#undef CFG_MONITOR_BASE /* 0x200000 to run ppcboot from RAM */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */
+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_SEME)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 12-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define MPC8XX_SPEED 50000000L
+#define MPC8XX_XIN 5000000L /* ref clk */
+#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
+#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
+#define CFG_SCCR (SCCR_TBS | SCCR_DFLCD001)
+
+
+/*-----------------------------------------------------------------------
+ * MAMR settings for SDRAM - 16-14
+ * => 0xC080200F
+ *-----------------------------------------------------------------------
+ * periodic timer for refresh
+ */
+#define CFG_MAMR_PTA 0xC0
+#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
+
+/*
+ * BR0 and OR0 (FLASH) used to re-map FLASH
+ */
+
+/* allow for max 8 MB of Flash */
+#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
+#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
+#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
+
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ */
+#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
+#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
+
+/* SDRAM timing: drive GPL5 high on first cycle */
+#define CFG_OR_TIMING_SDRAM (OR_G5LS)
+
+#define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2/OR2 - DIMM
+ */
+#define CFG_OR2 (OR_ACS_DIV4)
+#define CFG_BR2 (BR_MS_UPMA)
+
+/*
+ * BR3/OR3 - DIMM
+ */
+#define CFG_OR3 (OR_ACS_DIV4)
+#define CFG_BR3 (BR_MS_UPMA)
+
+/*
+ * BR4/OR4
+ */
+#define CFG_OR4 0
+#define CFG_BR4 0
+
+/*
+ * BR5/OR5
+ */
+#define CFG_OR5 0
+#define CFG_BR5 0
+
+/*
+ * BR6/OR6
+ */
+#define CFG_OR6 0
+#define CFG_BR6 0
+
+/*
+ * BR7/OR7
+ */
+#define CFG_OR7 0
+#define CFG_BR7 0
+
+
+/*-----------------------------------------------------------------------
+ * Debug Entry Mode
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CFG_MPTPR 0x00001900
#define CFG_PSRT 0x00000021
+#define CFG_RESET_ADDRESS 0x04400000
+
#endif /* __CONFIG_H */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
+
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */
#define INTEL_ID_28F320C3 0x88C588C5 /* 4MB , 8 8KB + 63 64KB bbt */
+#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
#define INTEL_ID_28F320JA3 0x00160016 /* 32M = 128K x 32 */
#define INTEL_ID_28F640JA3 0x00170017 /* 64M = 128K x 64 */
#define INTEL_ID_28F128JA3 0x00180018 /* 128M = 128K x 128 */
#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
+#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
+
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
void inline setenv (char *, char *);
int saveenv(void);
-#if defined(CONFIG_CPCI405) || \
- defined(CONFIG_AR405) || \
- defined(CONFIG_WALNUT405) || \
- defined(CONFIG_PIP405) || \
- defined(CONFIG_MIP405) || \
+#if defined(CONFIG_AR405) || \
+ defined(CONFIG_BAB750) || \
+ defined(CONFIG_CPCI405) || \
defined(CONFIG_CPCIISER4) || \
- defined(CONFIG_OCRTC) || \
defined(CONFIG_DASA_SIM) || \
defined(CONFIG_DU405) || \
defined(CONFIG_ERIC) || \
+ defined(CONFIG_MIP405) || \
defined(CONFIG_MOUSSE) || \
- defined(CONFIG_BAB750) || \
- defined(CONFIG_W7O)
-/* $(CPU)/405gp_pci.c */
+ defined(CONFIG_OCRTC) || \
+ defined(CONFIG_PIP405) || \
+ defined(CONFIG_SANDPOINT) || \
+ defined(CONFIG_W7O) || \
+ defined(CONFIG_WALNUT405)
void pci_init (bd_t *);
void pciinfo (int);
#endif
#ifdef CONFIG_HERMES
/* $(BOARD)/hermes.c */
-void hermes_set_led (int);
-void hermes_show_led_err (int);
-void hermes_flash_led (void);
void hermes_start_lxt980 (int speed);
#endif
int pcmcia_init (void);
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress (int status);
+#endif
+
#endif /* _PPCBOOT_H_ */
projects / users / rw / ppcboot.git / commitdiff