}
 
        /* Configure FLASH */
-       chipsize = b47n->nand_chip.chipsize >> 20;
+       chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20;
        tbits = ffs(chipsize); /* find first bit set */
        if (!tbits || tbits != fls(chipsize)) {
                pr_err("Invalid flash size: 0x%lX\n", chipsize);
 
        mtd->erasesize <<= 1;
        mtd->writesize <<= 1;
        mtd->oobsize <<= 1;
-       chip->chipsize <<= 1;
        chip->page_shift += 1;
        chip->phys_erase_shift += 1;
        chip->bbt_erase_shift += 1;
 
        dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
                chip->numchips);
        dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
-               chip->chipsize);
+               nanddev_target_size(&chip->base));
        dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
                chip->pagemask);
        dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n",
 
        dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
                                                        chip->numchips);
        dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
-                                                       chip->chipsize);
+               nanddev_target_size(&chip->base));
        dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
                                                        chip->pagemask);
        dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__,
 
        dev_dbg(dev, "Transcribing bad block marks...\n");
 
        /* Compute the number of blocks in the entire medium. */
-       block_count = chip->chipsize >> chip->phys_erase_shift;
+       block_count = nanddev_eraseblocks_per_target(&chip->base);
 
        /*
         * Loop over all the blocks in the medium, transcribing block marks as
 
                /* Update size of the MTD. */
                chip->numchips++;
                memorg->ntargets++;
-               mtd->size += chip->chipsize;
+               mtd->size += nanddev_target_size(&chip->base);
        }
 
        dev_info(&pdev->dev, "Found chip %zu on bank %i\n", chipnr, bank);
 
                mtd->oobsize = memorg->oobsize;
 
                memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
-               chip->chipsize = (uint64_t)type->chipsize << 20;
                memorg->eraseblocks_per_lun =
                        DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
                                           memorg->pagesize *
        int busw, ret;
        u8 *id_data = chip->id.data;
        u8 maf_id, dev_id;
+       u64 targetsize;
 
        /*
         * Let's start by initializing memorg fields that might be left
        if (!chip->parameters.model)
                return -ENOMEM;
 
-       chip->chipsize = (uint64_t)type->chipsize << 20;
-
        if (!type->pagesize)
                nand_manufacturer_detect(chip);
        else
        /* Calculate the address shift from the page size */
        chip->page_shift = ffs(mtd->writesize) - 1;
        /* Convert chipsize to number of pages per chip -1 */
-       chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+       targetsize = nanddev_target_size(&chip->base);
+       chip->pagemask = (targetsize >> chip->page_shift) - 1;
 
        chip->bbt_erase_shift = chip->phys_erase_shift =
                ffs(mtd->erasesize) - 1;
-       if (chip->chipsize & 0xffffffff)
-               chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
+       if (targetsize & 0xffffffff)
+               chip->chip_shift = ffs((unsigned)targetsize) - 1;
        else {
-               chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
+               chip->chip_shift = ffs((unsigned)(targetsize >> 32));
                chip->chip_shift += 32 - 1;
        }
 
        pr_info("%s %s\n", nand_manufacturer_name(manufacturer),
                chip->parameters.model);
        pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
-               (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
+               (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
                mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
        return 0;
 
        /* Store the number of chips and calc total size for mtd */
        memorg->ntargets = i;
        chip->numchips = i;
-       mtd->size = i * chip->chipsize;
+       mtd->size = i * nanddev_target_size(&chip->base);
 
        return 0;
 }
 
                        struct nand_bbt_descr *td, int chip)
 {
        struct mtd_info *mtd = nand_to_mtd(this);
+       u64 targetsize = nanddev_target_size(&this->base);
        int res = 0, i;
 
        if (td->options & NAND_BBT_PERCHIP) {
                for (i = 0; i < this->numchips; i++) {
                        if (chip == -1 || chip == i)
                                res = read_bbt(this, buf, td->pages[i],
-                                       this->chipsize >> this->bbt_erase_shift,
+                                       targetsize >> this->bbt_erase_shift,
                                        td, offs);
                        if (res)
                                return res;
-                       offs += this->chipsize >> this->bbt_erase_shift;
+                       offs += targetsize >> this->bbt_erase_shift;
                }
        } else {
                res = read_bbt(this, buf, td->pages[0],
 static int create_bbt(struct nand_chip *this, uint8_t *buf,
                      struct nand_bbt_descr *bd, int chip)
 {
+       u64 targetsize = nanddev_target_size(&this->base);
        struct mtd_info *mtd = nand_to_mtd(this);
        int i, numblocks, numpages;
        int startblock;
                               chip + 1, this->numchips);
                        return -EINVAL;
                }
-               numblocks = this->chipsize >> this->bbt_erase_shift;
+               numblocks = targetsize >> this->bbt_erase_shift;
                startblock = chip * numblocks;
                numblocks += startblock;
                from = (loff_t)startblock << this->bbt_erase_shift;
 static int search_bbt(struct nand_chip *this, uint8_t *buf,
                      struct nand_bbt_descr *td)
 {
+       u64 targetsize = nanddev_target_size(&this->base);
        struct mtd_info *mtd = nand_to_mtd(this);
        int i, chips;
        int startblock, block, dir;
        /* Do we have a bbt per chip? */
        if (td->options & NAND_BBT_PERCHIP) {
                chips = this->numchips;
-               bbtblocks = this->chipsize >> this->bbt_erase_shift;
+               bbtblocks = targetsize >> this->bbt_erase_shift;
                startblock &= bbtblocks - 1;
        } else {
                chips = 1;
                                break;
                        }
                }
-               startblock += this->chipsize >> this->bbt_erase_shift;
+               startblock += targetsize >> this->bbt_erase_shift;
        }
        /* Check, if we found a bbt for each requested chip */
        for (i = 0; i < chips; i++) {
 static int get_bbt_block(struct nand_chip *this, struct nand_bbt_descr *td,
                         struct nand_bbt_descr *md, int chip)
 {
+       u64 targetsize = nanddev_target_size(&this->base);
        int startblock, dir, page, numblocks, i;
 
        /*
                return td->pages[chip] >>
                                (this->bbt_erase_shift - this->page_shift);
 
-       numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
+       numblocks = (int)(targetsize >> this->bbt_erase_shift);
        if (!(td->options & NAND_BBT_PERCHIP))
                numblocks *= this->numchips;
 
                     struct nand_bbt_descr *td, struct nand_bbt_descr *md,
                     int chipsel)
 {
+       u64 targetsize = nanddev_target_size(&this->base);
        struct mtd_info *mtd = nand_to_mtd(this);
        struct erase_info einfo;
        int i, res, chip = 0;
                rcode = 0xff;
        /* Write bad block table per chip rather than per device? */
        if (td->options & NAND_BBT_PERCHIP) {
-               numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
+               numblocks = (int)(targetsize >> this->bbt_erase_shift);
                /* Full device write or specific chip? */
                if (chipsel == -1) {
                        nrchips = this->numchips;
  */
 static void mark_bbt_region(struct nand_chip *this, struct nand_bbt_descr *td)
 {
+       u64 targetsize = nanddev_target_size(&this->base);
        struct mtd_info *mtd = nand_to_mtd(this);
        int i, j, chips, block, nrblocks, update;
        uint8_t oldval;
        /* Do we have a bbt per chip? */
        if (td->options & NAND_BBT_PERCHIP) {
                chips = this->numchips;
-               nrblocks = (int)(this->chipsize >> this->bbt_erase_shift);
+               nrblocks = (int)(targetsize >> this->bbt_erase_shift);
        } else {
                chips = 1;
                nrblocks = (int)(mtd->size >> this->bbt_erase_shift);
  */
 static void verify_bbt_descr(struct nand_chip *this, struct nand_bbt_descr *bd)
 {
+       u64 targetsize = nanddev_target_size(&this->base);
        struct mtd_info *mtd = nand_to_mtd(this);
        u32 pattern_len;
        u32 bits;
        }
 
        if (bd->options & NAND_BBT_PERCHIP)
-               table_size = this->chipsize >> this->bbt_erase_shift;
+               table_size = targetsize >> this->bbt_erase_shift;
        else
                table_size = mtd->size >> this->bbt_erase_shift;
        table_size >>= 3;
 
        /* Please reference to the comment for nand_flash_detect_onfi. */
        memorg->eraseblocks_per_lun =
                1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
-       chip->chipsize = memorg->eraseblocks_per_lun;
-       chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
        memorg->bits_per_cell = p->bits_per_cell;
 
        if (le16_to_cpu(p->features) & JEDEC_FEATURE_16_BIT_BUS)
 
        memorg->eraseblocks_per_lun =
                1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
        memorg->max_bad_eraseblocks_per_lun = le32_to_cpu(p->blocks_per_lun);
-       chip->chipsize = memorg->eraseblocks_per_lun;
-       chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
        memorg->bits_per_cell = p->bits_per_cell;
 
        if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS)
 
        if (overridesize) {
                uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
                struct nand_memory_organization *memorg;
+               u64 targetsize;
 
                memorg = nanddev_get_memorg(&chip->base);
 
                        retval = -EINVAL;
                        goto err_exit;
                }
+
                /* N.B. This relies on nand_scan not doing anything with the size before we change it */
                nsmtd->size = new_size;
                memorg->eraseblocks_per_lun = 1 << overridesize;
-               chip->chipsize = new_size;
+               targetsize = nanddev_target_size(&chip->base);
                chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
-               chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+               chip->pagemask = (targetsize >> chip->page_shift) - 1;
        }
 
        if ((retval = setup_wear_reporting(nsmtd)) != 0)
 
 
 static int flctl_chip_attach_chip(struct nand_chip *chip)
 {
+       u64 targetsize = nanddev_target_size(&chip->base);
        struct mtd_info *mtd = nand_to_mtd(chip);
        struct sh_flctl *flctl = mtd_to_flctl(mtd);
 
 
        if (mtd->writesize == 512) {
                flctl->page_size = 0;
-               if (chip->chipsize > (32 << 20)) {
+               if (targetsize > (32 << 20)) {
                        /* big than 32MB */
                        flctl->rw_ADRCNT = ADRCNT_4;
                        flctl->erase_ADRCNT = ADRCNT_3;
-               } else if (chip->chipsize > (2 << 16)) {
+               } else if (targetsize > (2 << 16)) {
                        /* big than 128KB */
                        flctl->rw_ADRCNT = ADRCNT_3;
                        flctl->erase_ADRCNT = ADRCNT_2;
                }
        } else {
                flctl->page_size = 1;
-               if (chip->chipsize > (128 << 20)) {
+               if (targetsize > (128 << 20)) {
                        /* big than 128MB */
                        flctl->rw_ADRCNT = ADRCNT2_E;
                        flctl->erase_ADRCNT = ADRCNT_3;
-               } else if (chip->chipsize > (8 << 16)) {
+               } else if (targetsize > (8 << 16)) {
                        /* big than 512KB */
                        flctl->rw_ADRCNT = ADRCNT_4;
                        flctl->erase_ADRCNT = ADRCNT_2;
 
  *                           ONFI compliant or deduced from the datasheet if
  *                           the NAND chip is not ONFI compliant.
  * @numchips:          [INTERN] number of physical chips
- * @chipsize:          [INTERN] the size of one chip for multichip arrays
  * @pagemask:          [INTERN] page number mask = number of (pages / chip) - 1
  * @data_buf:          [INTERN] buffer for data, size is (page size + oobsize).
  * @pagecache:         Structure containing page cache related fields
        int bbt_erase_shift;
        int chip_shift;
        int numchips;
-       uint64_t chipsize;
        int pagemask;
        u8 *data_buf;