select SND_SOC_SOF_TIGERLAKE   if SND_SOC_SOF_TIGERLAKE_SUPPORT
        select SND_SOC_SOF_ELKHARTLAKE if SND_SOC_SOF_ELKHARTLAKE_SUPPORT
        select SND_SOC_SOF_JASPERLAKE  if SND_SOC_SOF_JASPERLAKE_SUPPORT
+       select SND_SOC_SOF_ALDERLAKE   if SND_SOC_SOF_ALDERLAKE_SUPPORT
        help
          This option is not user-selectable but automagically handled by
          'select' statements at a higher level.
          This option is not user-selectable but automagically handled by
          'select' statements at a higher level.
 
+config SND_SOC_SOF_ALDERLAKE_SUPPORT
+       bool "SOF support for Alderlake"
+       help
+         This adds support for Sound Open Firmware for Intel(R) platforms
+         using the Alderlake processors.
+         Say Y if you have such a device.
+         If unsure select "N".
+
+config SND_SOC_SOF_ALDERLAKE
+       tristate
+       select SND_SOC_SOF_HDA_COMMON
+       help
+         This option is not user-selectable but automagically handled by
+         'select' statements at a higher level
+
 config SND_SOC_SOF_HDA_COMMON
        tristate
        select SND_INTEL_DSP_CONFIG
 
 extern const struct sof_intel_dsp_desc tglh_chip_info;
 extern const struct sof_intel_dsp_desc ehl_chip_info;
 extern const struct sof_intel_dsp_desc jsl_chip_info;
+extern const struct sof_intel_dsp_desc adls_chip_info;
 
 /* machine driver select */
 void hda_machine_select(struct snd_sof_dev *sdev);
 
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
+
+const struct sof_intel_dsp_desc adls_chip_info = {
+       /* Alderlake-S */
+       .cores_num = 2,
+       .init_core_mask = BIT(0),
+       .host_managed_cores_mask = BIT(0),
+       .ipc_req = CNL_DSP_REG_HIPCIDR,
+       .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
+       .ipc_ack = CNL_DSP_REG_HIPCIDA,
+       .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
+       .ipc_ctl = CNL_DSP_REG_HIPCCTL,
+       .rom_init_timeout       = 300,
+       .ssp_count = ICL_SSP_COUNT,
+       .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+};
+EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
 };
 #endif
 
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_ALDERLAKE)
+static const struct sof_dev_desc adls_desc = {
+       .machines               = snd_soc_acpi_intel_hda_machines,
+       .resindex_lpe_base      = 0,
+       .resindex_pcicfg_base   = -1,
+       .resindex_imr_base      = -1,
+       .irqindex_host_ipc      = -1,
+       .resindex_dma_base      = -1,
+       .chip_info = &adls_chip_info,
+       .default_fw_path = "intel/sof",
+       .default_tplg_path = "intel/sof-tplg",
+       .default_fw_filename = "sof-adl-s.ri",
+       .nocodec_tplg_filename = "sof-adl-nocodec.tplg",
+       .ops = &sof_tgl_ops,
+};
+#endif
+
 static const struct dev_pm_ops sof_pci_pm = {
        .prepare = snd_sof_prepare,
        .complete = snd_sof_complete,
                .driver_data = (unsigned long)&ehl_desc},
        { PCI_DEVICE(0x8086, 0x4b58),
                .driver_data = (unsigned long)&ehl_desc},
+#endif
+#if IS_ENABLED(CONFIG_SND_SOC_SOF_ALDERLAKE)
+       { PCI_DEVICE(0x8086, 0x7ad0),
+               .driver_data = (unsigned long)&adls_desc},
 #endif
        { 0, }
 };