u32 isar;
        u32 ilcr;
        u32 iwcr;
+       u32 fm;
+       u32 hs;
 };
 
 enum pxa_i2c_types {
        unsigned char           master_code;
        unsigned long           rate;
        bool                    highmode_enter;
+       u32                     fm_mask;
+       u32                     hs_mask;
 };
 
 #define _IBMR(i2c)     ((i2c)->reg_ibmr)
                writel(i2c->slave_addr, _ISAR(i2c));
 
        /* set control register values */
-       writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
-       writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
+       writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
+       writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
 
 #ifdef CONFIG_I2C_PXA_SLAVE
        dev_info(&i2c->adap.dev, "Enabling slave mode\n");
        i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
        i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
        i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
+       i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM;
+       i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS;
+
        if (i2c_type != REGS_CE4100)
                i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;