* list of controller registers to be saved and restored during a
  * suspend/resume cycle.
  */
+static __initdata unsigned long exynos4210_clk_save[] = {
+       E4210_SRC_IMAGE,
+       E4210_SRC_LCD1,
+       E4210_SRC_MASK_LCD1,
+       E4210_DIV_LCD1,
+       E4210_GATE_IP_IMAGE,
+       E4210_GATE_IP_LCD1,
+       E4210_GATE_IP_PERIR,
+       E4210_MPLL_CON0,
+};
+
+static __initdata unsigned long exynos4x12_clk_save[] = {
+       E4X12_GATE_IP_IMAGE,
+       E4X12_GATE_IP_PERIR,
+       E4X12_SRC_CAM1,
+       E4X12_DIV_ISP,
+       E4X12_DIV_CAM1,
+       E4X12_MPLL_CON0,
+};
+
 static __initdata unsigned long exynos4_clk_regs[] = {
        SRC_LEFTBUS,
        DIV_LEFTBUS,
                        panic("%s: unable to determine soc\n", __func__);
        }
 
-       samsung_clk_init(np, reg_base, nr_clks,
-               exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs));
+       if (exynos4_soc == EXYNOS4210)
+               samsung_clk_init(np, reg_base, nr_clks,
+                       exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+                       exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
+       else
+               samsung_clk_init(np, reg_base, nr_clks,
+                       exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+                       exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
 
        if (np)
                samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
 
        }
 
        samsung_clk_init(np, reg_base, nr_clks,
-                       exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs));
+                       exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
+                       NULL, 0);
        samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
                        ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
                        ext_clk_match);
 
                return;
        }
 
-       samsung_clk_init(np, reg_base, nr_clks, NULL, 0);
+       samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
        samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
                ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
 
 
 /* setup the essentials required to support clock lookup using ccf */
 void __init samsung_clk_init(struct device_node *np, void __iomem *base,
                unsigned long nr_clks, unsigned long *rdump,
-               unsigned long nr_rdump)
+               unsigned long nr_rdump, unsigned long *soc_rdump,
+               unsigned long nr_soc_rdump)
 {
        reg_base = base;
 
        if (rdump && nr_rdump) {
                unsigned int idx;
                reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
-                                       * nr_rdump, GFP_KERNEL);
+                               * (nr_rdump + nr_soc_rdump), GFP_KERNEL);
                if (!reg_dump) {
                        pr_err("%s: memory alloc for register dump failed\n",
                                        __func__);
 
                for (idx = 0; idx < nr_rdump; idx++)
                        reg_dump[idx].offset = rdump[idx];
-               nr_reg_dump = nr_rdump;
+               for (idx = 0; idx < nr_soc_rdump; idx++)
+                       reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
+               nr_reg_dump = nr_rdump + nr_soc_rdump;
                register_syscore_ops(&samsung_clk_syscore_ops);
        }
 #endif
 
 
 extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
                unsigned long nr_clks, unsigned long *rdump,
-               unsigned long nr_rdump);
+               unsigned long nr_rdump, unsigned long *soc_rdump,
+               unsigned long nr_soc_rdump);
 extern void __init samsung_clk_of_register_fixed_ext(
                struct samsung_fixed_rate_clock *fixed_rate_clk,
                unsigned int nr_fixed_rate_clk,